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10 lines
328 B
Text
10 lines
328 B
Text
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This is a simple example for Yosys synthesis targeting the ZED FPGA
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development board [1, 2]. Simple script for xst-based synthesis (incl.
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generation of reference edif files) and uploading to the board can be
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found here [3].
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[1] http://www.zedboard.org/
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[2] https://www.xilinx.com/zynq/
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[3] http://verilog.james.walms.co.uk/
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