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https://github.com/YosysHQ/yosys
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215a777eb3
Renamed python script so that it sits next to the testbench file when alphabetically sorted. Reverted `MAX_WIDTH` to full precision for truncation testing.
84 lines
2.2 KiB
Verilog
84 lines
2.2 KiB
Verilog
module TB(input clk);
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parameter ADDRESS_WIDTH = 10;
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parameter ADDRESS_WIDTH_A = ADDRESS_WIDTH;
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parameter ADDRESS_WIDTH_B = ADDRESS_WIDTH;
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parameter DATA_WIDTH = 36;
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parameter DATA_WIDTH_A = DATA_WIDTH;
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parameter DATA_WIDTH_B = DATA_WIDTH;
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parameter VECTORLEN = 16;
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parameter SHIFT_VAL = 0;
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// intentionally keep expected values at full width precision to allow testing
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// of truncation
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localparam MAX_WIDTH = 36;
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reg rce_a_testvector [VECTORLEN-1:0];
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reg [ADDRESS_WIDTH_A-1:0] ra_a_testvector [VECTORLEN-1:0];
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reg [MAX_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0];
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reg wce_a_testvector [VECTORLEN-1:0];
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reg [ADDRESS_WIDTH_A-1:0] wa_a_testvector [VECTORLEN-1:0];
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reg [DATA_WIDTH_A-1:0] wd_a_testvector [VECTORLEN-1:0];
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reg rce_b_testvector [VECTORLEN-1:0];
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reg [ADDRESS_WIDTH_B-1:0] ra_b_testvector [VECTORLEN-1:0];
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reg [MAX_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0];
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reg wce_b_testvector [VECTORLEN-1:0];
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reg [ADDRESS_WIDTH_B-1:0] wa_b_testvector [VECTORLEN-1:0];
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reg [DATA_WIDTH_B-1:0] wd_b_testvector [VECTORLEN-1:0];
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reg [$clog2(VECTORLEN)-1:0] i = 0;
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integer j;
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initial begin
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for (j = 0; j < VECTORLEN; j = j + 1) begin
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rce_a_testvector[j] = 1'b0;
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ra_a_testvector[j] = 10'h0;
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wce_a_testvector[j] = 1'b0;
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wa_a_testvector[j] = 10'h0;
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rce_b_testvector[j] = 1'b0;
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ra_b_testvector[j] = 10'h0;
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wce_b_testvector[j] = 1'b0;
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wa_b_testvector[j] = 10'h0;
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end
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`MEM_TEST_VECTOR
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end
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wire rce_a = rce_a_testvector[i];
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wire [ADDRESS_WIDTH_A-1:0] ra_a = ra_a_testvector[i];
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wire [MAX_WIDTH-1:0] rq_a_e = rq_a_expected[i];
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wire [DATA_WIDTH_A-1:0] rq_a;
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wire wce_a = wce_a_testvector[i];
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wire [ADDRESS_WIDTH_A-1:0] wa_a = wa_a_testvector[i];
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wire [DATA_WIDTH_A-1:0] wd_a = wd_a_testvector[i];
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wire rce_b = rce_b_testvector[i];
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wire [ADDRESS_WIDTH_B-1:0] ra_b = ra_b_testvector[i];
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wire [MAX_WIDTH-1:0] rq_b_e = rq_b_expected[i];
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wire [DATA_WIDTH_B-1:0] rq_b;
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wire wce_b = wce_b_testvector[i];
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wire [ADDRESS_WIDTH_B-1:0] wa_b = wa_b_testvector[i];
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wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i];
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`UUT_SUBMODULE
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always @(posedge clk) begin
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if (i < VECTORLEN-1) begin
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if (i > 0) begin
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if($past(rce_a))
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assert(rq_a == rq_a_e);
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if($past(rce_b))
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assert(rq_b == rq_b_e);
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end
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i <= i + 1;
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end
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end
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endmodule
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