Eddie Hung 0671ae7d79 Merge pull request #1661 from YosysHQ/eddie/abc9_required ... abc9: add support for required times		2020-02-05 18:59:40 +01:00
..
tests	xilinx: Add simulation model for DSP48 (Virtex 4).	2020-01-29 01:40:00 +01:00
.gitignore
abc9_map.v	Adding (* techmap_autopurge *) to FD* in abc9_map.v	2020-01-14 12:22:21 -08:00
abc9_model.v	Merge branch 'eddie/abc9_refactor' into eddie/abc9_required	2020-01-27 12:29:28 -08:00
abc9_unmap.v	Merge remote-tracking branch 'origin/master' into xaig_dff	2020-01-06 15:02:44 -08:00
abc9_xc7.box	abc9_ops -prep_times: generate flop boxes from abc9_required attr	2020-01-10 14:49:52 -08:00
abc9_xc7.lut
abc9_xc7_nowide.lut
arith_map.v	Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623	2020-01-17 12:02:46 -08:00
brams_init.py
cells_map.v
cells_sim.v	Merge pull request #1661 from YosysHQ/eddie/abc9_required	2020-02-05 18:59:40 +01:00
cells_xtra.py	Merge pull request #1661 from YosysHQ/eddie/abc9_required	2020-02-05 18:59:40 +01:00
cells_xtra.v	Merge pull request #1661 from YosysHQ/eddie/abc9_required	2020-02-05 18:59:40 +01:00
lut_map.v	xilinx/ice40/ecp5: undo permuting LUT masks in lut_map	2020-01-27 13:30:27 -08:00
lutrams.txt	xilinx: use RAM32M/RAM64M for memories with two read ports	2020-02-02 14:34:21 +01:00
lutrams_map.v
Makefile.inc
mux_map.v	Change synth_xilinx's -nomux to -minmuxf <int>	2019-06-24 10:04:01 -07:00
synth_xilinx.cc	Add opt_lut_ins pass. (#1673)	2020-02-03 14:57:17 +01:00
xc3s_mult_map.v	xilinx: Support multiplier mapping for all families.	2019-10-22 18:06:57 +02:00
xc3sda_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_brams.txt
xc6s_brams_map.v
xc6s_dsp_map.v
xc6s_ff_map.v
xc7_brams_map.v
xc7_dsp_map.v	xilinx: Support multiplier mapping for all families.	2019-10-22 18:06:57 +02:00
xc7_ff_map.v	xilinx: Improve flip-flop handling.	2019-12-18 13:43:43 +01:00
xc7_xcu_brams.txt
xcu_brams_map.v
xcu_dsp_map.v	xilinx: Support multiplier mapping for all families.	2019-10-22 18:06:57 +02:00
xcup_urams.txt
xcup_urams_map.v
xilinx_dffopt.cc