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14 lines
423 B
Systemverilog
14 lines
423 B
Systemverilog
// 128-bit register with 16-bit lane writes indexed by a 3-bit selector (VPS).
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module opt_vps_wide (
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input logic clk,
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input logic wr_en,
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input logic [2:0] lane,
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input logic [15:0] wdata,
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output logic [127:0] q
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);
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logic [127:0] reg_data;
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always_ff @(posedge clk)
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if (wr_en)
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reg_data[((lane + 1) * 16) - 1 -: 16] <= wdata;
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assign q = reg_data;
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endmodule
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