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16 lines
407 B
Systemverilog
16 lines
407 B
Systemverilog
// Reference for VPS read: uses right-shift instead of variable part-select.
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module opt_vps_read (
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input logic clk,
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input logic wr_en,
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input logic [7:0] index,
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input logic [255:0] wdata,
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output logic [31:0] q
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);
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logic [255:0] reg_data;
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always_ff @(posedge clk)
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if (wr_en)
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reg_data <= wdata;
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assign q = (reg_data >> index);
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endmodule
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