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https://github.com/YosysHQ/yosys
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139 lines
2.5 KiB
Verilog
139 lines
2.5 KiB
Verilog
module $__ANALOGDEVICES_LUTRAM_ (...);
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parameter INIT = 0;
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parameter OPTION_SIZE = 32;
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parameter OPTION_MODE = "SP";
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parameter ABITS = 5;
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parameter WIDTH = 1;
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output PORT_RW_RD_DATA;
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input PORT_RW_WR_DATA;
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input [ABITS-1:0] PORT_RW_ADDR;
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input PORT_RW_WR_EN;
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input PORT_RW_CLK;
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output PORT_R_RD_DATA;
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input [ABITS-1:0] PORT_R_ADDR;
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generate
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if (OPTION_MODE=="SP")
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case(OPTION_SIZE)
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32:
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RAMS32X1
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#(
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.INIT(INIT)
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)
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_TECHMAP_REPLACE_
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(
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.O(PORT_RW_RD_DATA),
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.A0(PORT_RW_ADDR[0]),
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.A1(PORT_RW_ADDR[1]),
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.A2(PORT_RW_ADDR[2]),
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.A3(PORT_RW_ADDR[3]),
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.A4(PORT_RW_ADDR[4]),
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.D(PORT_RW_WR_DATA),
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.WCLK(PORT_RW_CLK),
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.WE(PORT_RW_WR_EN)
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);
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64:
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RAMS64X1
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#(
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.INIT(INIT)
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)
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_TECHMAP_REPLACE_
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(
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.O(PORT_RW_RD_DATA),
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.A0(PORT_RW_ADDR[0]),
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.A1(PORT_RW_ADDR[1]),
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.A2(PORT_RW_ADDR[2]),
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.A3(PORT_RW_ADDR[3]),
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.A4(PORT_RW_ADDR[4]),
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.A5(PORT_RW_ADDR[5]),
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.D(PORT_RW_WR_DATA),
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.WCLK(PORT_RW_CLK),
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.WE(PORT_RW_WR_EN)
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);
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default:
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$error("invalid SIZE/MODE combination");
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endcase
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else if (OPTION_MODE=="DP")
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case (OPTION_SIZE)
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32:
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RAMD32X1
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#(
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.INIT(INIT)
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)
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_TECHMAP_REPLACE_
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(
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.DPO(PORT_R_RD_DATA),
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.SPO(PORT_RW_RD_DATA),
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.A0(PORT_RW_ADDR[0]),
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.A1(PORT_RW_ADDR[1]),
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.A2(PORT_RW_ADDR[2]),
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.A3(PORT_RW_ADDR[3]),
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.A4(PORT_RW_ADDR[4]),
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.D(PORT_RW_WR_DATA),
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.DPRA0(PORT_R_ADDR[0]),
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.DPRA1(PORT_R_ADDR[1]),
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.DPRA2(PORT_R_ADDR[2]),
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.DPRA3(PORT_R_ADDR[3]),
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.DPRA4(PORT_R_ADDR[4]),
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.WCLK(PORT_RW_CLK),
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.WE(PORT_RW_WR_EN)
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);
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64:
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RAMD64X1
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#(
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.INIT(INIT)
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)
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_TECHMAP_REPLACE_
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(
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.DPO(PORT_R_RD_DATA),
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.SPO(PORT_RW_RD_DATA),
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.A0(PORT_RW_ADDR[0]),
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.A1(PORT_RW_ADDR[1]),
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.A2(PORT_RW_ADDR[2]),
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.A3(PORT_RW_ADDR[3]),
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.A4(PORT_RW_ADDR[4]),
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.A5(PORT_RW_ADDR[5]),
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.D(PORT_RW_WR_DATA),
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.DPRA0(PORT_R_ADDR[0]),
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.DPRA1(PORT_R_ADDR[1]),
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.DPRA2(PORT_R_ADDR[2]),
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.DPRA3(PORT_R_ADDR[3]),
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.DPRA4(PORT_R_ADDR[4]),
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.DPRA5(PORT_R_ADDR[5]),
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.WCLK(PORT_RW_CLK),
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.WE(PORT_RW_WR_EN)
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);
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default:
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$error("invalid SIZE/MODE combination");
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endcase
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else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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endmodule
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module $__ANALOGDEVICES_LUTRAM_DP_ (...);
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parameter INIT = 0;
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parameter OPTION_SIZE = 32;
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parameter ABITS = 5;
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parameter WIDTH = 1;
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output PORT_RW_RD_DATA;
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input PORT_RW_WR_DATA;
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input [ABITS-1:0] PORT_RW_ADDR;
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input PORT_RW_WR_EN;
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input PORT_RW_CLK;
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output PORT_R_RD_DATA;
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input [ABITS-1:0] PORT_R_ADDR;
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generate
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endgenerate
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endmodule
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