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yosys/tests
History
Jim Lawson 171c425cf9 Fix FIRRTL to Verilog process instance subfield assignment. 
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
2019-02-25 16:18:13 -08:00
..
asicworld Fix FIRRTL to Verilog process instance subfield assignment. 2019-02-25 16:18:13 -08:00
bram Added support for (single-clock) transparent memories to bram tests 2016-11-01 10:03:13 +01:00
errors Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 2018-10-25 02:37:56 +03:00
fsm Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
hana Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
lut cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
memories Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
opt Fix WREDUCE on FF not fixing ARST_VALUE parameter. 2019-02-22 10:30:42 -08:00
realmath Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
sat Allow $size and $bits in verilog mode, actually check test case 2017-09-29 11:56:43 +02:00
share Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
simple Fix FIRRTL to Verilog process instance subfield assignment. 2019-02-25 16:18:13 -08:00
smv Progress in SMV back-end 2015-06-19 14:08:46 +02:00
sva Squelch a little more trailing whitespace 2018-12-29 12:46:54 +01:00
svinterfaces Add missing .gitignore 2018-12-06 07:29:37 +01:00
techmap Added read-enable to memory model 2015-09-25 12:23:11 +02:00
tools Fix FIRRTL to Verilog process instance subfield assignment. 2019-02-25 16:18:13 -08:00
unit Build hotfix in tests/unit/Makefile 2016-12-11 10:58:49 +01:00
various Address requested changes - don't require non-$ name. 2019-02-22 16:06:10 -08:00
vloghtb bugfix in blif front-end 2015-05-18 11:15:49 +02:00