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30 lines
770 B
Systemverilog
30 lines
770 B
Systemverilog
module top (input clk, reset, up, down, output reg [7:0] cnt);
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always @(posedge clk) begin
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if (reset)
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cnt <= 0;
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else if (up)
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cnt <= cnt + 1;
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else if (down)
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cnt <= cnt - 1;
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end
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default clocking @(posedge clk); endclocking
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default disable iff (reset);
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assert property (up |=> cnt == $past(cnt) + 8'd 1);
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assert property (up [*2] |=> cnt == $past(cnt, 2) + 8'd 2);
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assert property (up ##1 up |=> cnt == $past(cnt, 2) + 8'd 2);
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`ifndef FAIL
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assume property (down |-> !up);
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`endif
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assert property (up ##1 down |=> cnt == $past(cnt, 2));
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assert property (down |=> cnt == $past(cnt) - 8'd 1);
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property down_n(n);
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down [*n] |=> cnt == $past(cnt, n) - n;
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endproperty
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assert property (down_n(8'd 3));
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assert property (down_n(8'd 5));
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endmodule
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