mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 01:54:10 +00:00
Code Activity
yosys/backends/verilog
History
Catherine d9a4a42389 write_verilog: don't assign to a reg. 
Fixes #2035.
2024-04-03 13:06:45 +02:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc write_verilog: don't assign to a reg. 2024-04-03 13:06:45 +02:00