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yosys/backends/verilog
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Catherine d9a4a42389 write_verilog: don't assign to a reg. 
Fixes #2035.
2024-04-03 13:06:45 +02:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc write_verilog: don't assign to a reg. 2024-04-03 13:06:45 +02:00