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19 lines
256 B
Systemverilog
19 lines
256 B
Systemverilog
module top (
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input clk,
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input a, b, c, d
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);
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default clocking @(posedge clk); endclocking
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assert property (
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a ##[*] b |=> c until d
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);
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`ifndef FAIL
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assume property (
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b |=> ##5 d
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);
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assume property (
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b || (c && !d) |=> c
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);
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`endif
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endmodule
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