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110 lines
2 KiB
Verilog
110 lines
2 KiB
Verilog
`timescale 1ns/1ps
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/*
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This file contains analog / mixed signal cells, or other things that are not possible to fully model
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in behavioral Verilog.
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It also contains some stuff like oscillators that use non-synthesizeable constructs such as delays.
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TODO: do we want a third file for those cells?
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*/
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module GP_ABUF(input wire IN, output wire OUT);
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assign OUT = IN;
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//must be 1, 5, 20, 50
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//values >1 only available with Vdd > 2.7V
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parameter BANDWIDTH_KHZ = 1;
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endmodule
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module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
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parameter BANDWIDTH = "HIGH";
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parameter VIN_ATTEN = 1;
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parameter VIN_ISRC_EN = 0;
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parameter HYSTERESIS = 0;
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initial OUT = 0;
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endmodule
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module GP_BANDGAP(output reg OK);
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parameter AUTO_PWRDN = 1;
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parameter CHOPPER_EN = 1;
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parameter OUT_DELAY = 100;
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endmodule
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module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
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initial VOUT = 0;
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//analog hard IP is not supported for simulation
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endmodule
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module GP_LFOSC(input PWRDN, output reg CLKOUT);
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parameter PWRDN_EN = 0;
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parameter AUTO_PWRDN = 0;
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parameter OUT_DIV = 1;
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initial CLKOUT = 0;
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//auto powerdown not implemented for simulation
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//output dividers not implemented for simulation
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always begin
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if(PWRDN)
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CLKOUT = 0;
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else begin
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//half period of 1730 Hz
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#289017;
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CLKOUT = ~CLKOUT;
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end
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end
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endmodule
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module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
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parameter GAIN = 1;
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parameter INPUT_MODE = "SINGLE";
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initial VOUT = 0;
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//cannot simulate mixed signal IP
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endmodule
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module GP_PWRDET(output reg VDD_LOW);
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initial VDD_LOW = 0;
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endmodule
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module GP_VREF(input VIN, output reg VOUT);
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parameter VIN_DIV = 1;
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parameter VREF = 0;
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//cannot simulate mixed signal IP
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endmodule
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module GP_POR(output reg RST_DONE);
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parameter POR_TIME = 500;
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initial begin
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RST_DONE = 0;
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if(POR_TIME == 4)
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#4000;
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else if(POR_TIME == 500)
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#500000;
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else begin
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$display("ERROR: bad POR_TIME for GP_POR cell");
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$finish;
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end
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RST_DONE = 1;
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end
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endmodule
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