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			261 lines
		
	
	
	
		
			5.2 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			261 lines
		
	
	
	
		
			5.2 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
module GP_DFFS(input D, CLK, nSET, output reg Q);
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	parameter [0:0] INIT = 1'bx;
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	GP_DFFSR #(
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		.INIT(INIT),
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		.SRMODE(1'b1),
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	) _TECHMAP_REPLACE_ (
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		.D(D),
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		.CLK(CLK),
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		.nSR(nSET),
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		.Q(Q)
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	);
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endmodule
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module GP_DFFR(input D, CLK, nRST, output reg Q);
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	parameter [0:0] INIT = 1'bx;
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	GP_DFFSR #(
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		.INIT(INIT),
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		.SRMODE(1'b0),
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	) _TECHMAP_REPLACE_ (
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		.D(D),
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		.CLK(CLK),
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		.nSR(nRST),
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		.Q(Q)
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	);
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endmodule
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module GP_DFFSI(input D, CLK, nSET, output reg nQ);
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	parameter [0:0] INIT = 1'bx;
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	GP_DFFSRI #(
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		.INIT(INIT),
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		.SRMODE(1'b1),
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	) _TECHMAP_REPLACE_ (
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		.D(D),
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		.CLK(CLK),
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		.nSR(nSET),
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		.nQ(nQ)
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	);
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endmodule
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module GP_DFFRI(input D, CLK, nRST, output reg nQ);
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	parameter [0:0] INIT = 1'bx;
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	GP_DFFSRI #(
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		.INIT(INIT),
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		.SRMODE(1'b0),
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	) _TECHMAP_REPLACE_ (
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		.D(D),
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		.CLK(CLK),
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		.nSR(nRST),
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		.nQ(nQ)
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	);
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endmodule
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module GP_DLATCHS(input D, nCLK, nSET, output reg Q);
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	parameter [0:0] INIT = 1'bx;
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	GP_DLATCHSR #(
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		.INIT(INIT),
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		.SRMODE(1'b1),
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	) _TECHMAP_REPLACE_ (
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		.D(D),
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		.nCLK(nCLK),
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		.nSR(nSET),
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		.Q(Q)
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	);
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endmodule
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module GP_DLATCHR(input D, nCLK, nRST, output reg Q);
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	parameter [0:0] INIT = 1'bx;
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	GP_DLATCHSR #(
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		.INIT(INIT),
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		.SRMODE(1'b0),
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	) _TECHMAP_REPLACE_ (
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		.D(D),
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		.nCLK(nCLK),
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		.nSR(nRST),
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		.Q(Q)
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	);
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endmodule
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module GP_DLATCHSI(input D, nCLK, nSET, output reg nQ);
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	parameter [0:0] INIT = 1'bx;
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	GP_DLATCHSRI #(
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		.INIT(INIT),
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		.SRMODE(1'b1),
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	) _TECHMAP_REPLACE_ (
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		.D(D),
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		.nCLK(nCLK),
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		.nSR(nSET),
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		.nQ(nQ)
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	);
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endmodule
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module GP_DLATCHRI(input D, nCLK, nRST, output reg nQ);
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	parameter [0:0] INIT = 1'bx;
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	GP_DLATCHSRI #(
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		.INIT(INIT),
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		.SRMODE(1'b0),
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	) _TECHMAP_REPLACE_ (
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		.D(D),
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		.nCLK(nCLK),
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		.nSR(nRST),
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		.nQ(nQ)
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	);
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endmodule
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module GP_OBUFT(input IN, input OE, output OUT);
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	GP_IOBUF _TECHMAP_REPLACE_ (
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		.IN(IN),
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		.OE(OE),
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		.IO(OUT),
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		.OUT()
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	);
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endmodule
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module \$lut (A, Y);
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	parameter WIDTH = 0;
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	parameter LUT = 0;
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	(* force_downto *)
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	input [WIDTH-1:0] A;
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	output Y;
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	generate
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		if (WIDTH == 1) begin
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		if(LUT == 2'b01) begin
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			GP_INV _TECHMAP_REPLACE_ (.OUT(Y), .IN(A[0]) );
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		end
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		else begin
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			GP_2LUT #(.INIT({2'b00, LUT})) _TECHMAP_REPLACE_ (.OUT(Y),
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				.IN0(A[0]), .IN1(1'b0));
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		end
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		end else
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		if (WIDTH == 2) begin
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			GP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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				.IN0(A[0]), .IN1(A[1]));
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		end else
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		if (WIDTH == 3) begin
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			GP_3LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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				.IN0(A[0]), .IN1(A[1]), .IN2(A[2]));
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		end else
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		if (WIDTH == 4) begin
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			GP_4LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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				.IN0(A[0]), .IN1(A[1]), .IN2(A[2]), .IN3(A[3]));
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		end else begin
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			wire _TECHMAP_FAIL_ = 1;
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		end
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	endgenerate
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endmodule
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module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
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	input wire CE;
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	input wire CLK;
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	output reg OUT;
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	(* force_downto *)
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	output reg[WIDTH-1:0] POUT;
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	input wire RST;
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	input wire UP;
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	parameter COUNT_TO = 1;
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	parameter RESET_MODE = "RISING";
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	parameter RESET_TO_MAX = 0;
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	parameter HAS_POUT = 0;
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	parameter HAS_CE = 0;
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	parameter WIDTH = 8;
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	parameter DIRECTION = "DOWN";
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	//If we have a DIRECTION other than DOWN fail... GP_COUNTx_ADV is not supported yet
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	if(DIRECTION != "DOWN") begin
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		initial begin
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			$display("ERROR: \$__COUNT_ support for GP_COUNTx_ADV is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).");
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			$finish;
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		end
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	end
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	//If counter is more than 14 bits wide, complain (also shouldn't happen)
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	else if(WIDTH > 14) begin
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		initial begin
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			$display("ERROR: \$__COUNT_ support for cascaded counters is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).");
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			$finish;
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		end
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	end
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	//If counter is more than 8 bits wide and has parallel output, we have a problem
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	else if(WIDTH > 8 && HAS_POUT) begin
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		initial begin
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			$display("ERROR: \$__COUNT_ support for 9-14 bit counters with parallel output is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).");
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			$finish;
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		end
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	end
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	//Looks like a legal counter! Do something with it
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	else if(WIDTH <= 8) begin
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		if(HAS_CE) begin
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			wire ce_not;
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			GP_INV ceinv(
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				.IN(CE),
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				.OUT(ce_not)
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			);
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			GP_COUNT8_ADV #(
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				.COUNT_TO(COUNT_TO),
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				.RESET_MODE(RESET_MODE),
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				.RESET_VALUE(RESET_TO_MAX ? "COUNT_TO" : "ZERO"),
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				.CLKIN_DIVIDE(1)
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			) _TECHMAP_REPLACE_ (
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				.CLK(CLK),
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				.RST(RST),
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				.OUT(OUT),
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				.UP(1'b0),		//always count down for now
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				.KEEP(ce_not),
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				.POUT(POUT)
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			);
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		end
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		else begin
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			GP_COUNT8 #(
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				.COUNT_TO(COUNT_TO),
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				.RESET_MODE(RESET_MODE),
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				.CLKIN_DIVIDE(1)
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			) _TECHMAP_REPLACE_ (
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				.CLK(CLK),
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				.RST(RST),
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				.OUT(OUT),
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				.POUT(POUT)
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			);
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		end
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	end
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	else begin
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		if(HAS_CE) begin
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			wire ce_not;
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			GP_INV ceinv(
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				.IN(CE),
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				.OUT(ce_not)
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			);
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			GP_COUNT14_ADV #(
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				.COUNT_TO(COUNT_TO),
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				.RESET_MODE(RESET_TO_MAX ? "COUNT_TO" : "ZERO"),
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				.RESET_VALUE("COUNT_TO"),
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				.CLKIN_DIVIDE(1)
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			) _TECHMAP_REPLACE_ (
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				.CLK(CLK),
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				.RST(RST),
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				.OUT(OUT),
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				.UP(1'b0),		//always count down for now
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				.KEEP(ce_not),
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				.POUT(POUT)
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			);
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		end
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		else begin
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			GP_COUNT14 #(
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				.COUNT_TO(COUNT_TO),
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				.RESET_MODE(RESET_MODE),
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				.CLKIN_DIVIDE(1)
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			) _TECHMAP_REPLACE_ (
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				.CLK(CLK),
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				.RST(RST),
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				.OUT(OUT)
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			);
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		end
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	end
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endmodule
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