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Code Activity
yosys/frontends/vhdl2verilog
History
Clifford Wolf 6c84341f22 Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
..
Makefile.inc Added vhdl2verilog 2014-02-21 18:59:49 +01:00
vhdl2verilog.cc Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00