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Code
Activity
6c3d767976
yosys
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passes
History
Clifford Wolf
9e35021585
Addred sat option -ignore_unknown_cells
2014-02-03 16:26:10 +01:00
..
abc
Fixed use of limited length buffer in ABC blif parser
2013-12-31 21:58:35 +01:00
cmds
Added show -notitle option
2014-02-02 17:55:32 +01:00
extract
enabled multiple "-map" for the extract pass
2014-01-25 21:11:34 +01:00
fsm
Fixes in fsm detect/extract for better detection of non-fsm circuits
2013-12-06 12:53:20 +01:00
hierarchy
Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))
2014-01-14 20:12:45 +01:00
memory
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
2014-02-03 13:01:45 +01:00
opt
More opt_const -mux_bool features
2014-02-02 22:41:24 +01:00
proc
Tiny cleanup in proc_mux.cc
2014-01-03 16:54:59 +01:00
sat
Addred sat option -ignore_unknown_cells
2014-02-03 16:26:10 +01:00
scc
fixed typos
2013-03-18 07:28:31 +01:00
submod
Replaced RTLIL::Const::str with generic decoder method
2013-12-04 14:14:05 +01:00
techmap
Added support for // comments in liberty parser
2014-01-25 06:32:16 +01:00