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e833c6a418
- Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
29 lines
575 B
Verilog
29 lines
575 B
Verilog
module pass_through_a(
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input wire [31:0] inp,
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output wire [31:0] out
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);
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assign out[31:0] = inp[31:0];
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endmodule
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module top_a(
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input wire signed [31:0] inp,
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output wire signed [31:0] out
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);
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pass_through_a pt(inp[31:0], out[31:0]);
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endmodule
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// tests both module declaration orderings
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module top_b(
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input wire signed [31:0] inp,
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output wire signed [31:0] out
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);
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pass_through_b pt(inp[31:0], out[31:0]);
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endmodule
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module pass_through_b(
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input wire [31:0] inp,
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output wire [31:0] out
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);
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assign out[31:0] = inp[31:0];
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endmodule
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