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tests
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Improved xilinx "bram1" test
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2015-04-09 17:12:12 +02:00 |
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.gitignore
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Added support for initialized xilinx brams
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2015-04-06 17:07:10 +02:00 |
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abc.box
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Transpose CARRY4 delays
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2019-05-24 14:09:15 -07:00 |
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abc.lut
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Modify LUT area cost to be same as old abc
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2019-05-21 14:31:19 -07:00 |
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arith_map.v
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Instead of MUXCY/XORCY use CARRY4 (with timing)
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2019-05-21 16:19:45 -07:00 |
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brams.txt
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Added read-enable to memory model
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2015-09-25 12:23:11 +02:00 |
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brams_bb.v
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Added Xilinx bram black-box modules
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2015-04-06 08:44:30 +02:00 |
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brams_init.py
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Squelch trailing whitespace, including meta-whitespace
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2018-03-11 16:03:41 +01:00 |
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brams_map.v
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Revert BRAM WRITE_MODE changes.
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2019-03-04 09:22:22 -08:00 |
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cells_map.v
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Fix/workaround symptom unveiled by #1023
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2019-05-21 18:50:02 -07:00 |
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cells_sim.v
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Add whitebox support to DRAM
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2019-05-23 08:58:57 -07:00 |
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cells_xtra.sh
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Add whitebox support to DRAM
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2019-05-23 08:58:57 -07:00 |
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cells_xtra.v
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Add whitebox support to DRAM
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2019-05-23 08:58:57 -07:00 |
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drams.txt
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Add "min bits" and "min wports" to xilinx dram rules
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2019-05-23 11:32:28 -07:00 |
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drams_map.v
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Xilinx DRAMS: RAM64X1D, RAM128X1D
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2015-04-09 13:37:07 +02:00 |
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ff_map.v
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Move neg-pol to pos-pol mapping from ff_map to cells_map.v
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2019-04-28 12:36:04 -07:00 |
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lut_map.v
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Changes required for VPR place and route synth_xilinx.
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2019-03-01 12:02:27 -08:00 |
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Makefile.inc
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Cleanup, call pmux2shiftx even without -nosrl
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2019-04-22 12:14:37 -07:00 |
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synth_xilinx.cc
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Add whitebox support to DRAM
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2019-05-23 08:58:57 -07:00 |
