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Code Activity
yosys/frontends
History
Clifford Wolf e9fe57c75e Only allow posedge/negedge with 1 bit wide signals
2016-08-10 19:32:11 +02:00
..
ast Only allow posedge/negedge with 1 bit wide signals 2016-08-10 19:32:11 +02:00
blif Added "read_blif -sop" 2016-06-18 12:33:13 +02:00
ilang Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
liberty Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
verific Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
verilog Fixed bug in parsing real constants 2016-08-06 13:16:23 +02:00
vhdl2verilog Added "yosys -D" feature 2016-04-21 23:28:37 +02:00