whitequark 86f2804dc3 write_verilog: dump zero width sigspecs correctly. ... Before this commit, zero width sigspecs were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) PR #1203 has addressed this issue before, but in an incomplete way.		2021-12-11 12:01:52 +00:00
..
Makefile.inc	initial import	2013-01-05 11:13:26 +01:00
verilog_backend.cc	write_verilog: dump zero width sigspecs correctly.	2021-12-11 12:01:52 +00:00