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https://github.com/YosysHQ/yosys
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79 lines
1.5 KiB
Text
79 lines
1.5 KiB
Text
read_verilog <<EOT
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module wreduce_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (j >> 4) - i;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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opt_expr
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wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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##########
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read_verilog <<EOT
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module wreduce_sub_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = (j >>> 4) - i;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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opt_expr
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wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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##########
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# Testcase from: https://github.com/YosysHQ/yosys/commit/25680f6a078bb32f157bd580705656496717bafb
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design -reset
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read_verilog <<EOT
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module top(
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input clk,
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input rst,
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input [2:0] a,
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output [1:0] b
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);
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reg [2:0] b_reg;
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initial begin
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b_reg <= 3'b0;
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end
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assign b = b_reg[1:0];
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always @(posedge clk or posedge rst) begin
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if(rst) begin
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b_reg <= 3'b0;
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end else begin
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b_reg <= a;
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end
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end
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endmodule
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EOT
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proc
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wreduce
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select -assert-count 1 t:$adff r:ARST_VALUE=2'b00 %i
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