mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-30 19:22:31 +00:00
8611429237
* ABC9: RAMB36E1 Bug Patch * Add simplified testcase * Also fix xaiger writer for under-width output ports * Remove old testcase * Missing top-level input port * Fix tabs --------- Co-authored-by: Eddie Hung <eddie@fpgeh.com>
13 lines
471 B
Verilog
13 lines
471 B
Verilog
module bug3670(input we, output [31:0] o1, o2, output o3);
|
|
// Completely missing port connections, where first affected port
|
|
// (ADDRARDADDR) has a $setup delay
|
|
RAMB36E1 ram1(.DOADO(o1));
|
|
|
|
// Under-specified input port connections (WEA is 4 bits) which
|
|
// has a $setup delay
|
|
RAMB36E1 ram2(.WEA(we), .DOADO(o2));
|
|
|
|
// Under-specified output port connections (DOADO is 32 bits)
|
|
// with clk-to-q delay
|
|
RAMB36E1 ram3(.DOADO(o3));
|
|
endmodule
|