mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-30 19:22:31 +00:00
c2b7ad3b28
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
13 lines
279 B
Text
13 lines
279 B
Text
read_verilog ../common/blockram.v
|
|
hierarchy -top sync_ram_sp
|
|
proc
|
|
memory -nomap
|
|
equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
|
|
memory
|
|
opt -full
|
|
|
|
design -load postopt
|
|
cd sync_ram_sp
|
|
|
|
select -assert-count 1 t:EG_PHY_BRAM
|
|
select -assert-none t:EG_PHY_BRAM %% t:* %D
|