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https://github.com/YosysHQ/yosys
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72787f52fc
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
101 lines
3.4 KiB
Verilog
101 lines
3.4 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// ============================================================================
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// LUT mapping
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`ifndef _NO_LUTS
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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(* force_downto *)
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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if (LUT == 2'b01) begin
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INV _TECHMAP_REPLACE_ (.O(Y), .I(A[0]));
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end else begin
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LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]));
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end
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end else
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if (WIDTH == 2) begin
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LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]));
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end else
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if (WIDTH == 3) begin
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LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]));
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end else
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if (WIDTH == 4) begin
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LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]));
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end else
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if (WIDTH == 5 && WIDTH <= `LUT_WIDTH) begin
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LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]));
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end else
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if (WIDTH == 6 && WIDTH <= `LUT_WIDTH) begin
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LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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end else
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if (WIDTH == 5 && WIDTH > `LUT_WIDTH) begin
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wire f0, f1;
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\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
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\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
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MUXF5 mux5(.I0(f0), .I1(f1), .S(A[4]), .O(Y));
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end else
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if (WIDTH == 6 && WIDTH > `LUT_WIDTH) begin
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wire f0, f1;
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\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
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\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
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MUXF6 mux6(.I0(f0), .I1(f1), .S(A[5]), .O(Y));
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end else
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if (WIDTH == 7) begin
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wire f0, f1;
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\$lut #(.LUT(LUT[ 63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
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\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
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MUXF7 mux7(.I0(f0), .I1(f1), .S(A[6]), .O(Y));
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end else
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if (WIDTH == 8) begin
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wire f0, f1;
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\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
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\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
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MUXF8 mux8(.I0(f0), .I1(f1), .S(A[7]), .O(Y));
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end else
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if (WIDTH == 9) begin
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wire f0, f1;
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\$lut #(.LUT(LUT[255: 0]), .WIDTH(8)) lut0 (.A(A[7:0]), .Y(f0));
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\$lut #(.LUT(LUT[511:256]), .WIDTH(8)) lut1 (.A(A[7:0]), .Y(f1));
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MUXF9 mux9(.I0(f0), .I1(f1), .S(A[8]), .O(Y));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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`endif
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