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26 lines
746 B
Verilog
26 lines
746 B
Verilog
// Stub to invert M10K write-enable.
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module \$__MISTRAL_M10K (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter INIT = 0;
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 10;
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input CLK1;
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input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input A1EN, B1EN;
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output reg [CFG_DBITS-1:0] B1DATA;
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// Normal M10K configs use WREN[1], which is negative-true.
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// However, 8x40-bit mode uses WREN[0], which is positive-true.
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wire a1en;
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if (CFG_DBITS == 40)
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assign a1en = A1EN;
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else
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assign a1en = !A1EN;
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MISTRAL_M10K #(.INIT(INIT), .CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(a1en), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN));
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endmodule
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