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84 lines
4.1 KiB
Verilog
84 lines
4.1 KiB
Verilog
//////////////////////////////////////////////////////////////////
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// //
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// Generic Library SRAM with per byte write enable //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// Configurable depth and width. The DATA_WIDTH must be a //
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// multiple of 8. //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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// expect-wr-ports 1
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// expect-rd-ports 1
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module generic_sram_byte_en
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#(
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parameter DATA_WIDTH = 32,
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parameter ADDRESS_WIDTH = 4
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)
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(
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input i_clk,
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input [DATA_WIDTH-1:0] i_write_data,
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input i_write_enable,
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input [ADDRESS_WIDTH-1:0] i_address,
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input [DATA_WIDTH/8-1:0] i_byte_enable,
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output reg [DATA_WIDTH-1:0] o_read_data
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);
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reg [DATA_WIDTH-1:0] mem [0:2**ADDRESS_WIDTH-1];
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integer i;
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always @(posedge i_clk)
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begin
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// read
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o_read_data <= i_write_enable ? {DATA_WIDTH{1'd0}} : mem[i_address];
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// write
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if (i_write_enable)
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for (i=0;i<DATA_WIDTH/8;i=i+1)
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begin
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mem[i_address][i*8+0] <= i_byte_enable[i] ? i_write_data[i*8+0] : mem[i_address][i*8+0] ;
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mem[i_address][i*8+1] <= i_byte_enable[i] ? i_write_data[i*8+1] : mem[i_address][i*8+1] ;
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mem[i_address][i*8+2] <= i_byte_enable[i] ? i_write_data[i*8+2] : mem[i_address][i*8+2] ;
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mem[i_address][i*8+3] <= i_byte_enable[i] ? i_write_data[i*8+3] : mem[i_address][i*8+3] ;
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mem[i_address][i*8+4] <= i_byte_enable[i] ? i_write_data[i*8+4] : mem[i_address][i*8+4] ;
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mem[i_address][i*8+5] <= i_byte_enable[i] ? i_write_data[i*8+5] : mem[i_address][i*8+5] ;
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mem[i_address][i*8+6] <= i_byte_enable[i] ? i_write_data[i*8+6] : mem[i_address][i*8+6] ;
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mem[i_address][i*8+7] <= i_byte_enable[i] ? i_write_data[i*8+7] : mem[i_address][i*8+7] ;
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end
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end
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endmodule
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