mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
122 lines
3.7 KiB
C++
122 lines
3.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2019 Miodrag Milanovic <miodrag@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static SigBit get_bit_or_zero(const SigSpec &sig)
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{
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if (GetSize(sig) == 0)
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return State::S0;
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return sig[0];
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}
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static void fix_carry_chain(Module *module)
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{
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SigMap sigmap(module);
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pool<SigBit> ci_bits;
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dict<SigBit, SigBit> mapping_bits;
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for (auto cell : module->cells())
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{
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if (cell->type == "\\EFX_ADD") {
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SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0"));
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SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1"));
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if (bit_i0 == State::S0 && bit_i1== State::S0) {
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SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
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SigBit bit_o = sigmap(cell->getPort("\\O"));
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ci_bits.insert(bit_ci);
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mapping_bits[bit_ci] = bit_o;
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}
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}
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}
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vector<Cell*> adders_to_fix_cells;
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for (auto cell : module->cells())
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{
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if (cell->type == "\\EFX_ADD") {
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SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
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SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0"));
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SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1"));
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SigBit canonical_bit = sigmap(bit_ci);
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if (!ci_bits.count(canonical_bit))
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continue;
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if (bit_i0 == State::S0 && bit_i1== State::S0)
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continue;
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adders_to_fix_cells.push_back(cell);
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log("Found %s cell named %s with invalid CI signal.\n", log_id(cell->type), log_id(cell));
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}
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}
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for (auto cell : adders_to_fix_cells)
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{
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SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
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SigBit canonical_bit = sigmap(bit_ci);
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auto bit = mapping_bits.at(canonical_bit);
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log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
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Cell *c = module->addCell(NEW_ID, "\\EFX_ADD");
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SigBit new_bit = module->addWire(NEW_ID);
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c->setParam("\\I0_POLARITY", State::S1);
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c->setParam("\\I1_POLARITY", State::S1);
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c->setPort("\\I0", bit);
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c->setPort("\\I1", State::S1);
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c->setPort("\\CI", State::S0);
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c->setPort("\\CO", new_bit);
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cell->setPort("\\CI", new_bit);
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}
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}
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struct EfinixCarryFixPass : public Pass {
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EfinixCarryFixPass() : Pass("efinix_fixcarry", "Efinix: fix carry chain") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" efinix_fixcarry [options] [selection]\n");
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log("\n");
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log("Add Efinix adders to fix carry chain if needed.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing efinix_fixcarry pass (fix invalid carry chain).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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break;
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}
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extra_args(args, argidx, design);
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Module *module = design->top_module();
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if (module == nullptr)
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log_cmd_error("No top module found.\n");
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fix_carry_chain(module);
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}
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} EfinixCarryFixPass;
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PRIVATE_NAMESPACE_END
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