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18 lines
659 B
Text
18 lines
659 B
Text
read_verilog ../common/fsm.v
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hierarchy -top fsm
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proc
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flatten
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equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 1 t:AL_MAP_LUT2
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select -assert-count 5 t:AL_MAP_LUT5
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select -assert-count 1 t:AL_MAP_LUT6
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select -assert-count 6 t:AL_MAP_SEQ
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select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D
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