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yosys/tests/verilog/block_labels.ys
Kamil Rakoczy 98c4feb72f Add check of begin/end labels for genblock
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-02-04 17:16:30 +01:00

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read_verilog <<EOT
module foo;
genvar a = 0;
for (a = 0; a < 10; a++) begin : a
end : a
endmodule
EOT
read_verilog <<EOT
module foo2;
genvar a = 0;
for (a = 0; a < 10; a++) begin : a
end
endmodule
EOT
logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1
read_verilog <<EOT
module foo3;
genvar a = 0;
for (a = 0; a < 10; a++) begin : a
end : b
endmodule
EOT