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61 lines
2.4 KiB
Text
61 lines
2.4 KiB
Text
read_verilog <<EOT
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module foo(
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input [7:0] A,
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input [7:0] B,
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input [7:0] C,
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input [7:0] D,
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output reg [7:0] X,
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output reg [7:0] Y);
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assign X = A * B;
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assign Y = C * D;
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endmodule
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EOT
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synth_quicklogic -dspv2 -run :map_dsp
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# this is just taken from map_dsp step
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wreduce t:$mul
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ql_dsp_macc -dspv2
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techmap -map +/mul2dsp.v -map +/quicklogic/qlf_k6n10f/dspv2_map.v -D USE_DSP_CFG_PARAMS=0 -D DSP_SIGNEDONLY -D DSP_A_MAXWIDTH=32 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__MUL32X18
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chtype -set $mul t:$__soft_mul
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techmap -map +/mul2dsp.v -map +/quicklogic/qlf_k6n10f/dspv2_map.v -D USE_DSP_CFG_PARAMS=0 -D DSP_SIGNEDONLY -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__MUL16X9
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# TODO is this missing from synth_quicklogic?
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read_verilog -lib +/quicklogic/qlf_k6n10f/dspv2_sim.v
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select -assert-count 2 t:dspv2_16x9x32_cfg_ports
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select -assert-count 0 t:dspv2_32x18x64_cfg_ports
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equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv2_sim.v ql_dsp_simd -dspv2
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design -load postopt
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select -assert-count 0 t:dspv2_16x9x32_cfg_ports
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select -assert-count 1 t:dspv2_32x18x64_cfg_ports
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design -reset
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read_verilog <<EOT
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module foo(
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input [7:0] A,
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input [7:0] B,
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input [7:0] C,
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input [7:0] D,
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input [7:0] E,
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output reg [7:0] X,
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output reg [7:0] Y);
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assign X = A * B;
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assign Y = C * (D + E); // <-- look here
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endmodule
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EOT
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synth_quicklogic -dspv2 -run :map_dsp
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wreduce t:$mul
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ql_dsp_macc -dspv2
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techmap -map +/mul2dsp.v -map +/quicklogic/qlf_k6n10f/dspv2_map.v -D USE_DSP_CFG_PARAMS=0 -D DSP_SIGNEDONLY -D DSP_A_MAXWIDTH=32 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__MUL32X18
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chtype -set $mul t:$__soft_mul
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techmap -map +/mul2dsp.v -map +/quicklogic/qlf_k6n10f/dspv2_map.v -D USE_DSP_CFG_PARAMS=0 -D DSP_SIGNEDONLY -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__MUL16X9
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# TODO is this missing from synth_quicklogic?
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read_verilog -lib +/quicklogic/qlf_k6n10f/dspv2_sim.v
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select -assert-count 2 t:dspv2_16x9x32_cfg_ports
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select -assert-count 0 t:dspv2_32x18x64_cfg_ports
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equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv2_sim.v ql_dsp_simd -dspv2
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design -load postopt
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select -assert-count 0 t:dspv2_16x9x32_cfg_ports
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select -assert-count 1 t:dspv2_32x18x64_cfg_ports
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