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31 lines
675 B
Text
31 lines
675 B
Text
read_verilog << EOT
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`default_nettype none
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module top (
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input wire clk,
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input wire [9:0] rd_addr,
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output reg [15:0] rd_data,
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input wire [9:0] wr_addr,
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input wire [15:0] wr_data,
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input wire wr_en
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);
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(* ram_style = "block" *) reg [15:0] mem [0:1023];
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// Read port — separate always block
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always @(posedge clk) begin
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rd_data <= mem[rd_addr];
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end
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// Write port — separate always block
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always @(posedge clk) begin
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if (wr_en)
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mem[wr_addr] <= wr_data;
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end
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endmodule
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EOT
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synth_gowin -top top
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splitnets
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select -assert-any top/mem.0.0 %ci*:+DPX9B[ADA]:+DFF:+IBUF i:wr_en %i
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