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yosys/frontends/verilog
Kaj Tuomi 48ddbe52fb Read bigger Verilog files.
Hit parser limit with 3M gate design. This commit fix it.
2019-05-18 14:20:30 +03:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc
Makefile.inc Read bigger Verilog files. 2019-05-18 14:20:30 +03:00
preproc.cc
verilog_frontend.cc
verilog_frontend.h
verilog_lexer.l
verilog_parser.y Merge pull request #1013 from antmicro/parameter_attributes 2019-05-16 14:21:18 +02:00