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Code Activity
yosys/examples/intel
History
Clifford Wolf b72a7e1104 Replace CRLF line endings with LF in de2i.qsf (quartus example)
2017-04-12 16:51:46 +02:00
..
asicworld_lfsr Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs 2017-04-05 23:01:29 -05:00
DE2i-150 Replace CRLF line endings with LF in de2i.qsf (quartus example) 2017-04-12 16:51:46 +02:00
MAX10 Squelch trailing whitespace 2017-04-12 15:11:09 +02:00