Clifford Wolf 65f91e5120 Rename "write_verilog -nobasenradix" to "write_verilog -decimal"		2017-10-03 17:31:21 +02:00
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a10gx
common
cycloneiv
cycloneive
cyclonev
max10
Makefile.inc
synth_intel.cc	Rename "write_verilog -nobasenradix" to "write_verilog -decimal"	2017-10-03 17:31:21 +02:00