Krystine Sherwin 657b0bd92b documenting.rst: literalinclude cell doc examples ... Add a sed command to the (top level) makefile for extract comment block for the specified cell. Works with both simlib.v and simcells.v (by abusing `%` pattern matching slightly to disambiguate which to search).		2025-11-18 12:20:33 +13:00
..
extending_yosys	documenting.rst: literalinclude cell doc examples	2025-11-18 12:20:33 +13:00
flow	docs: fix verilog frontend internals	2025-08-11 13:34:10 +02:00
formats	Docs: Move rtlil_text (back) to appendix	2024-10-15 07:34:52 +13:00
hashing.rst	pyosys: rewrite using pybind11	2025-10-03 11:54:44 +03:00
index.rst	Docs: Move verilog.rst to using_yosys	2025-08-05 09:53:58 +12:00
techmap.rst	Docs: Reflow line length	2024-10-15 07:23:45 +13:00