mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 11:42:30 +00:00 
			
		
		
		
	
		
			
				
	
	
		
			17 lines
		
	
	
	
		
			350 B
		
	
	
	
		
			Text
		
	
	
	
	
	
			
		
		
	
	
			17 lines
		
	
	
	
		
			350 B
		
	
	
	
		
			Text
		
	
	
	
	
	
| logger -expect error "Cannot add interface port `\\i' because a signal with the same name was already created" 1
 | |
| read_verilog -sv <<EOT
 | |
| interface intf;
 | |
|     logic x;
 | |
|     assign x = 1;
 | |
|     modport m(input x);
 | |
| endinterface
 | |
| module mod(intf.m i);
 | |
|     wire x;
 | |
|     assign x = i.x;
 | |
|     wire i;
 | |
| endmodule
 | |
| module top;
 | |
|     intf i();
 | |
|     mod m(i);
 | |
| endmodule
 | |
| EOT
 |