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32 lines
575 B
Text
32 lines
575 B
Text
read_verilog <<EOT
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module test_module (
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a,
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b,
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x,
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y
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);
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input [0:0] a;
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output [0:0] b;
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input [1:0] x;
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output [1:0] y;
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assign b = a;
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assign y = x;
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endmodule
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EOT
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proc
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splitnets -ports -format __:
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select -assert-count 0 w:a;
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select -assert-count 1 w:a_0_;
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select -assert-count 0 w:a_1_;
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select -assert-count 0 w:b;
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select -assert-count 1 w:b_0_;
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select -assert-count 0 w:b_1_;
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select -assert-count 0 w:x;
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select -assert-count 1 w:x_0_;
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select -assert-count 1 w:x_1_;
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select -assert-count 0 w:y;
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select -assert-count 1 w:y_0_;
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select -assert-count 1 w:y_1_;
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