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123 lines
3.7 KiB
Verilog
123 lines
3.7 KiB
Verilog
//----------------------------------------------------
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// A four level, round-robin arbiter. This was
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// orginally coded by WD Peterson in VHDL.
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//----------------------------------------------------
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module arbiter (
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clk,
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rst,
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req3,
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req2,
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req1,
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req0,
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gnt3,
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gnt2,
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gnt1,
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gnt0
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);
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// --------------Port Declaration-----------------------
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input clk;
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input rst;
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input req3;
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input req2;
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input req1;
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input req0;
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output gnt3;
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output gnt2;
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output gnt1;
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output gnt0;
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//--------------Internal Registers----------------------
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wire [1:0] gnt ;
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wire comreq ;
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wire beg ;
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wire [1:0] lgnt ;
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wire lcomreq ;
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reg lgnt0 ;
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reg lgnt1 ;
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reg lgnt2 ;
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reg lgnt3 ;
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reg lasmask ;
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reg lmask0 ;
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reg lmask1 ;
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reg ledge ;
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//--------------Code Starts Here-----------------------
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always @ (posedge clk)
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if (rst) begin
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lgnt0 <= 0;
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lgnt1 <= 0;
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lgnt2 <= 0;
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lgnt3 <= 0;
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end else begin
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lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)
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| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0)
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| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0)
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| (~lcomreq & lmask1 & lmask0 & req0 )
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| ( lcomreq & lgnt0 );
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lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1)
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| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0)
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| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0)
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| (~lcomreq & lmask1 & lmask0 & req1 & ~req0)
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| ( lcomreq & lgnt1);
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lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1)
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| (~lcomreq & ~lmask1 & lmask0 & req2)
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| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0)
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| (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0)
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| ( lcomreq & lgnt2);
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lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1)
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| (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2)
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| (~lcomreq & lmask1 & ~lmask0 & req3)
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| (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0)
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| ( lcomreq & lgnt3);
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end
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//----------------------------------------------------
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// lasmask state machine.
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//----------------------------------------------------
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assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;
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always @ (posedge clk)
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begin
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lasmask <= (beg & ~ledge & ~lasmask);
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ledge <= (beg & ~ledge & lasmask)
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| (beg & ledge & ~lasmask);
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end
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//----------------------------------------------------
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// comreq logic.
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//----------------------------------------------------
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assign lcomreq = ( req3 & lgnt3 )
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| ( req2 & lgnt2 )
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| ( req1 & lgnt1 )
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| ( req0 & lgnt0 );
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//----------------------------------------------------
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// Encoder logic.
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//----------------------------------------------------
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assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
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//----------------------------------------------------
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// lmask register.
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//----------------------------------------------------
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always @ (posedge clk )
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if( rst ) begin
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lmask1 <= 0;
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lmask0 <= 0;
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end else if(lasmask) begin
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lmask1 <= lgnt[1];
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lmask0 <= lgnt[0];
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end else begin
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lmask1 <= lmask1;
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lmask0 <= lmask0;
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end
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assign comreq = lcomreq;
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assign gnt = lgnt;
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//----------------------------------------------------
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// Drive the outputs
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//----------------------------------------------------
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assign gnt3 = lgnt3;
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assign gnt2 = lgnt2;
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assign gnt1 = lgnt1;
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assign gnt0 = lgnt0;
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endmodule
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