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https://github.com/YosysHQ/yosys
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41 lines
No EOL
1.5 KiB
Text
41 lines
No EOL
1.5 KiB
Text
# ISC License
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#
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# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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read_verilog <<EOT
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module widemux(
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input [3:0] data,
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input S0,
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input S1,
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output Y
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);
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assign Y = S1 ? (S0 ? data[3] : data[1]) : (S0 ? data[2] : data[0]);
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endmodule
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EOT
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synth_microchip -top widemux -family polarfire -noiopad
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select -assert-count 1 t:MX4
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select -assert-none t:MX4 %% t:* %D
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# RTL style is different here forming a different structure
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read_verilog ../common/mux.v
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design -save read
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hierarchy -top mux4
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proc
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equiv_opt -assert -map +/microchip/cells_sim.v synth_microchip -top mux4 -family polarfire -noiopad
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 3 t:CFG3
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select -assert-none t:CFG3 %% t:* %D |