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https://github.com/YosysHQ/yosys
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225 lines
5.8 KiB
Verilog
225 lines
5.8 KiB
Verilog
module $__XILINX_BLOCKRAM_TDP_ (...);
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parameter INIT = 0;
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parameter OPTION_MODE = "FULL";
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parameter OPTION_HAS_RDFIRST = 0;
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parameter PORT_A_RD_WIDTH = 1;
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parameter PORT_A_WR_WIDTH = 1;
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parameter PORT_A_WR_EN_WIDTH = 1;
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parameter PORT_A_RD_USED = 1;
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parameter PORT_A_WR_USED = 1;
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parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE";
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parameter PORT_A_RD_INIT_VALUE = 0;
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parameter PORT_A_RD_SRST_VALUE = 1;
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parameter PORT_B_RD_WIDTH = 1;
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parameter PORT_B_WR_WIDTH = 1;
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parameter PORT_B_WR_EN_WIDTH = 1;
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parameter PORT_B_RD_USED = 0;
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parameter PORT_B_WR_USED = 0;
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parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE";
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parameter PORT_B_RD_INIT_VALUE = 0;
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parameter PORT_B_RD_SRST_VALUE = 0;
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input [15:0] PORT_A_ADDR;
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input [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA;
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input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
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output [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA;
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input PORT_A_RD_SRST;
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input [15:0] PORT_B_ADDR;
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input [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA;
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input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
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output [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA;
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input PORT_B_RD_SRST;
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`include "brams_defs.vh"
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`define PARAMS_COMMON \
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.WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \
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.WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \
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.READ_WIDTH_A(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), \
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.READ_WIDTH_B(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), \
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.WRITE_WIDTH_A(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), \
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.WRITE_WIDTH_B(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), \
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.DOA_REG(0), \
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.DOB_REG(0), \
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.INIT_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_INIT_VALUE)), \
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.INIT_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_INIT_VALUE)), \
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.SRVAL_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_SRST_VALUE)), \
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.SRVAL_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_SRST_VALUE)),
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`define PORTS_COMMON \
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.DOUTADOUT(DO_A), \
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.DOUTPADOUTP(DOP_A), \
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.DINADIN(DI_A), \
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.DINPADINP(DIP_A), \
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.DOUTBDOUT(DO_B), \
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.DOUTPBDOUTP(DOP_B), \
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.DINBDIN(DI_B), \
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.DINPBDINP(DIP_B), \
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.CLKARDCLK(PORT_A_CLK), \
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.CLKBWRCLK(PORT_B_CLK), \
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.ENARDEN(PORT_A_CLK_EN), \
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.ENBWREN(PORT_B_CLK_EN), \
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.REGCEAREGCE(1'b0), \
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.REGCEB(1'b0), \
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.ADDRENA(1'b1), \
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.ADDRENB(1'b1), \
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.RSTRAMARSTRAM(PORT_A_RD_SRST), \
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.RSTRAMB(PORT_B_RD_SRST), \
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.RSTREGARSTREG(1'b0), \
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.RSTREGB(1'b0), \
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.WEA(WE_A), \
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.WEBWE(WE_B), \
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.ADDRARDADDR(PORT_A_ADDR), \
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.ADDRBWRADDR(PORT_B_ADDR), \
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.SLEEP(1'b0),
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`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA)
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`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA)
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`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA)
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`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA)
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wire [3:0] WE_A = {4{PORT_A_WR_EN}};
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wire [3:0] WE_B = {4{PORT_B_WR_EN}};
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generate
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if (OPTION_MODE == "HALF") begin
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RAMB18E2 #(
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`PARAMS_INIT_18
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`PARAMS_INITP_18
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`PARAMS_COMMON
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) _TECHMAP_REPLACE_ (
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`PORTS_COMMON
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);
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end else if (OPTION_MODE == "FULL") begin
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RAMB36E2 #(
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`PARAMS_INIT_36
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`PARAMS_INITP_36
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`PARAMS_COMMON
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) _TECHMAP_REPLACE_ (
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`PORTS_COMMON
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);
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end
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endgenerate
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endmodule
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module $__XILINX_BLOCKRAM_SDP_ (...);
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parameter INIT = 0;
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parameter OPTION_MODE = "FULL";
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parameter OPTION_WRITE_MODE = "READ_FIRST";
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parameter PORT_W_WIDTH = 1;
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parameter PORT_W_WR_EN_WIDTH = 1;
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parameter PORT_W_USED = 1;
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parameter PORT_R_WIDTH = 1;
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parameter PORT_R_USED = 0;
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parameter PORT_R_RD_INIT_VALUE = 0;
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parameter PORT_R_RD_SRST_VALUE = 0;
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input PORT_W_CLK;
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input PORT_W_CLK_EN;
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input [15:0] PORT_W_ADDR;
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input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
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input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
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input PORT_R_CLK;
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input PORT_R_CLK_EN;
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input [15:0] PORT_R_ADDR;
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output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
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input PORT_R_RD_SRST;
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`include "brams_defs.vh"
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`define PARAMS_COMMON \
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.WRITE_MODE_A(OPTION_WRITE_MODE), \
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.WRITE_MODE_B(OPTION_WRITE_MODE), \
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.READ_WIDTH_A(PORT_R_USED ? PORT_R_WIDTH : 0), \
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.READ_WIDTH_B(0), \
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.WRITE_WIDTH_A(0), \
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.WRITE_WIDTH_B(PORT_W_USED ? PORT_W_WIDTH : 0), \
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.DOA_REG(0), \
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.DOB_REG(0),
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`define PORTS_COMMON \
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.CLKBWRCLK(PORT_W_CLK), \
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.CLKARDCLK(PORT_R_CLK), \
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.ENBWREN(PORT_W_CLK_EN), \
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.ENARDEN(PORT_R_CLK_EN), \
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.REGCEAREGCE(1'b0), \
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.REGCEB(1'b0), \
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.ADDRENA(1'b1), \
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.ADDRENB(1'b1), \
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.RSTRAMARSTRAM(PORT_R_RD_SRST), \
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.RSTRAMB(1'b0), \
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.RSTREGARSTREG(1'b0), \
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.RSTREGB(1'b0), \
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.WEA(0), \
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.WEBWE(PORT_W_WR_EN), \
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.ADDRARDADDR(PORT_R_ADDR), \
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.ADDRBWRADDR(PORT_W_ADDR), \
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.SLEEP(1'b0),
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`MAKE_DI(DI, DIP, PORT_W_WR_DATA)
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`MAKE_DO(DO, DOP, PORT_R_RD_DATA)
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generate
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if (OPTION_MODE == "HALF") begin
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RAMB18E2 #(
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`PARAMS_INIT_18
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`PARAMS_INITP_18
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`PARAMS_COMMON
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.INIT_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)),
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.INIT_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[35:18]) : 0),
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.SRVAL_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)),
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.SRVAL_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[35:18]) : 0),
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) _TECHMAP_REPLACE_ (
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`PORTS_COMMON
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.DOUTADOUT(DO[15:0]),
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.DOUTBDOUT(DO[31:16]),
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.DOUTPADOUTP(DOP[1:0]),
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.DOUTPBDOUTP(DOP[3:2]),
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.DINADIN(DI[15:0]),
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.DINBDIN(PORT_W_WIDTH == 36 ? DI[31:16] : DI[15:0]),
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.DINPADINP(DIP[1:0]),
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.DINPBDINP(PORT_W_WIDTH == 36 ? DIP[3:2] : DIP[1:0]),
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);
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end else if (OPTION_MODE == "FULL") begin
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RAMB36E2 #(
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`PARAMS_INIT_36
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`PARAMS_INITP_36
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`PARAMS_COMMON
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.INIT_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)),
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.INIT_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[71:36]) : 0),
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.SRVAL_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)),
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.SRVAL_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[71:36]) : 0),
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) _TECHMAP_REPLACE_ (
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`PORTS_COMMON
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.DOUTADOUT(DO[31:0]),
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.DOUTBDOUT(DO[63:32]),
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.DOUTPADOUTP(DOP[3:0]),
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.DOUTPBDOUTP(DOP[7:4]),
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.DINADIN(DI[31:0]),
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.DINBDIN(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]),
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.DINPADINP(DIP[3:0]),
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.DINPBDINP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]),
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);
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end
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endgenerate
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endmodule
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