mirror of
https://github.com/YosysHQ/yosys
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51 lines
1.8 KiB
Verilog
51 lines
1.8 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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(* techmap_celltype = "$_DFFE_[NP][NP][01][NP]_" *)
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module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
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parameter _TECHMAP_CELLTYPE_ = "";
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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CC_DFF #(
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.CLK_INV(_TECHMAP_CELLTYPE_[39:32] == "N"),
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.EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
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.SR_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
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.SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1"),
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.INIT(_TECHMAP_WIREINIT_Q_)
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) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(R), .Q(Q));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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(* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *)
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module \$_DLATCH_xxx_ (input E, R, D, output Q);
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parameter _TECHMAP_CELLTYPE_ = "";
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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CC_DLT #(
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.G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
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.SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
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.SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1"),
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.INIT(_TECHMAP_WIREINIT_Q_)
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) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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