mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 19:52:31 +00:00
459 lines
9.7 KiB
Verilog
459 lines
9.7 KiB
Verilog
// LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7, Ultrascale.
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// The definitions are in lutrams_xc5v.txt.
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module $__ANALOGDEVICES_LUTRAM_SP_ (...);
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parameter INIT = 0;
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parameter OPTION_ABITS = 5;
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parameter WIDTH = 8;
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parameter BITS_USED = 0;
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output [WIDTH-1:0] PORT_RW_RD_DATA;
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input [WIDTH-1:0] PORT_RW_WR_DATA;
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input [OPTION_ABITS-1:0] PORT_RW_ADDR;
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input PORT_RW_WR_EN;
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input PORT_RW_CLK;
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function [(1 << OPTION_ABITS)-1:0] init_slice;
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input integer idx;
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integer i;
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for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
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init_slice[i] = INIT[i * WIDTH + idx];
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endfunction
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function [(2 << OPTION_ABITS)-1:0] init_slice2;
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input integer idx;
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integer i;
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for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
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init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
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endfunction
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generate
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case(OPTION_ABITS)
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5: if (WIDTH == 8)
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RAM32M
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#(
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.INIT_D(init_slice2(0)),
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.INIT_C(init_slice2(1)),
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.INIT_B(init_slice2(2)),
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.INIT_A(init_slice2(3)),
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)
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_TECHMAP_REPLACE_
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(
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.DOA(PORT_RW_RD_DATA[7:6]),
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.DOB(PORT_RW_RD_DATA[5:4]),
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.DOC(PORT_RW_RD_DATA[3:2]),
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.DOD(PORT_RW_RD_DATA[1:0]),
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.DIA(PORT_RW_WR_DATA[7:6]),
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.DIB(PORT_RW_WR_DATA[5:4]),
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.DIC(PORT_RW_WR_DATA[3:2]),
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.DID(PORT_RW_WR_DATA[1:0]),
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.ADDRA(PORT_RW_ADDR),
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.ADDRB(PORT_RW_ADDR),
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.ADDRC(PORT_RW_ADDR),
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.ADDRD(PORT_RW_ADDR),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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);
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else
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RAM32M16
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#(
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.INIT_H(init_slice2(0)),
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.INIT_G(init_slice2(1)),
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.INIT_F(init_slice2(2)),
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.INIT_E(init_slice2(3)),
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.INIT_D(init_slice2(4)),
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.INIT_C(init_slice2(5)),
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.INIT_B(init_slice2(6)),
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.INIT_A(init_slice2(7)),
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)
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_TECHMAP_REPLACE_
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(
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.DOA(PORT_RW_RD_DATA[15:14]),
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.DOB(PORT_RW_RD_DATA[13:12]),
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.DOC(PORT_RW_RD_DATA[11:10]),
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.DOD(PORT_RW_RD_DATA[9:8]),
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.DOE(PORT_RW_RD_DATA[7:6]),
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.DOF(PORT_RW_RD_DATA[5:4]),
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.DOG(PORT_RW_RD_DATA[3:2]),
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.DOH(PORT_RW_RD_DATA[1:0]),
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.DIA(PORT_RW_WR_DATA[15:14]),
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.DIB(PORT_RW_WR_DATA[13:12]),
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.DIC(PORT_RW_WR_DATA[11:10]),
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.DID(PORT_RW_WR_DATA[9:8]),
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.DIE(PORT_RW_WR_DATA[7:6]),
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.DIF(PORT_RW_WR_DATA[5:4]),
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.DIG(PORT_RW_WR_DATA[3:2]),
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.DIH(PORT_RW_WR_DATA[1:0]),
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.ADDRA(PORT_RW_ADDR),
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.ADDRB(PORT_RW_ADDR),
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.ADDRC(PORT_RW_ADDR),
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.ADDRD(PORT_RW_ADDR),
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.ADDRE(PORT_RW_ADDR),
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.ADDRF(PORT_RW_ADDR),
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.ADDRG(PORT_RW_ADDR),
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.ADDRH(PORT_RW_ADDR),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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);
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6: begin
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genvar i;
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for (i = 0; i < WIDTH; i = i + 1)
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if (BITS_USED[i])
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RAM64X1S
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#(
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.INIT(init_slice(i)),
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)
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slice
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(
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.A0(PORT_RW_ADDR[0]),
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.A1(PORT_RW_ADDR[1]),
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.A2(PORT_RW_ADDR[2]),
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.A3(PORT_RW_ADDR[3]),
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.A4(PORT_RW_ADDR[4]),
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.A5(PORT_RW_ADDR[5]),
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.D(PORT_RW_WR_DATA[i]),
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.O(PORT_RW_RD_DATA[i]),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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);
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end
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default:
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$error("invalid OPTION_ABITS/WIDTH combination");
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endcase
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endgenerate
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endmodule
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module $__ANALOGDEVICES_LUTRAM_DP_ (...);
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parameter INIT = 0;
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parameter OPTION_ABITS = 5;
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parameter WIDTH = 4;
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parameter BITS_USED = 0;
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output [WIDTH-1:0] PORT_RW_RD_DATA;
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input [WIDTH-1:0] PORT_RW_WR_DATA;
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input [OPTION_ABITS-1:0] PORT_RW_ADDR;
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input PORT_RW_WR_EN;
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input PORT_RW_CLK;
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output [WIDTH-1:0] PORT_R_RD_DATA;
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input [OPTION_ABITS-1:0] PORT_R_ADDR;
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function [(1 << OPTION_ABITS)-1:0] init_slice;
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input integer idx;
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integer i;
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for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
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init_slice[i] = INIT[i * WIDTH + idx];
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endfunction
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function [(2 << OPTION_ABITS)-1:0] init_slice2;
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input integer idx;
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integer i;
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for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
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init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
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endfunction
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generate
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case (OPTION_ABITS)
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5: if (WIDTH == 4)
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RAM32M
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#(
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.INIT_D(init_slice2(0)),
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.INIT_C(init_slice2(0)),
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.INIT_B(init_slice2(1)),
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.INIT_A(init_slice2(1)),
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)
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_TECHMAP_REPLACE_
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(
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.DOA(PORT_R_RD_DATA[3:2]),
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.DOB(PORT_RW_RD_DATA[3:2]),
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.DOC(PORT_R_RD_DATA[1:0]),
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.DOD(PORT_RW_RD_DATA[1:0]),
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.DIA(PORT_RW_WR_DATA[3:2]),
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.DIB(PORT_RW_WR_DATA[3:2]),
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.DIC(PORT_RW_WR_DATA[1:0]),
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.DID(PORT_RW_WR_DATA[1:0]),
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.ADDRA(PORT_R_ADDR),
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.ADDRB(PORT_RW_ADDR),
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.ADDRC(PORT_R_ADDR),
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.ADDRD(PORT_RW_ADDR),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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);
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else
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RAM32M16
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#(
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.INIT_H(init_slice2(0)),
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.INIT_G(init_slice2(0)),
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.INIT_F(init_slice2(1)),
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.INIT_E(init_slice2(1)),
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.INIT_D(init_slice2(2)),
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.INIT_C(init_slice2(2)),
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.INIT_B(init_slice2(3)),
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.INIT_A(init_slice2(3)),
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)
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_TECHMAP_REPLACE_
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(
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.DOA(PORT_R_RD_DATA[7:6]),
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.DOB(PORT_RW_RD_DATA[7:6]),
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.DOC(PORT_R_RD_DATA[5:4]),
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.DOD(PORT_RW_RD_DATA[5:4]),
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.DOE(PORT_R_RD_DATA[3:2]),
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.DOF(PORT_RW_RD_DATA[3:2]),
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.DOG(PORT_R_RD_DATA[1:0]),
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.DOH(PORT_RW_RD_DATA[1:0]),
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.DIA(PORT_RW_WR_DATA[7:6]),
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.DIB(PORT_RW_WR_DATA[7:6]),
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.DIC(PORT_RW_WR_DATA[5:4]),
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.DID(PORT_RW_WR_DATA[5:4]),
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.DIE(PORT_RW_WR_DATA[3:2]),
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.DIF(PORT_RW_WR_DATA[3:2]),
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.DIG(PORT_RW_WR_DATA[1:0]),
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.DIH(PORT_RW_WR_DATA[1:0]),
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.ADDRA(PORT_R_ADDR),
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.ADDRB(PORT_RW_ADDR),
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.ADDRC(PORT_R_ADDR),
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.ADDRD(PORT_RW_ADDR),
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.ADDRE(PORT_R_ADDR),
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.ADDRF(PORT_RW_ADDR),
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.ADDRG(PORT_R_ADDR),
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.ADDRH(PORT_RW_ADDR),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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);
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6: begin
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genvar i;
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for (i = 0; i < WIDTH; i = i + 1)
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if (BITS_USED[i])
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RAM64X1D
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#(
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.INIT(init_slice(i)),
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)
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slice
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(
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.A0(PORT_RW_ADDR[0]),
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.A1(PORT_RW_ADDR[1]),
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.A2(PORT_RW_ADDR[2]),
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.A3(PORT_RW_ADDR[3]),
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.A4(PORT_RW_ADDR[4]),
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.A5(PORT_RW_ADDR[5]),
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.D(PORT_RW_WR_DATA[i]),
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.SPO(PORT_RW_RD_DATA[i]),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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.DPRA0(PORT_R_ADDR[0]),
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.DPRA1(PORT_R_ADDR[1]),
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.DPRA2(PORT_R_ADDR[2]),
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.DPRA3(PORT_R_ADDR[3]),
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.DPRA4(PORT_R_ADDR[4]),
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.DPRA5(PORT_R_ADDR[5]),
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.DPO(PORT_R_RD_DATA[i]),
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);
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end
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7: begin
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genvar i;
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for (i = 0; i < WIDTH; i = i + 1)
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if (BITS_USED[i])
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RAM128X1D
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#(
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.INIT(init_slice(i)),
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)
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slice
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(
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.A(PORT_RW_ADDR),
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.D(PORT_RW_WR_DATA[i]),
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.SPO(PORT_RW_RD_DATA[i]),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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.DPRA(PORT_R_ADDR),
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.DPO(PORT_R_RD_DATA[i]),
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);
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end
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8: begin
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genvar i;
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for (i = 0; i < WIDTH; i = i + 1)
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if (BITS_USED[i])
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RAM256X1D
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#(
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.INIT(init_slice(i)),
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)
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slice
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(
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.A(PORT_RW_ADDR),
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.D(PORT_RW_WR_DATA[i]),
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.SPO(PORT_RW_RD_DATA[i]),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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.DPRA(PORT_R_ADDR),
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.DPO(PORT_R_RD_DATA[i]),
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);
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end
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default:
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$error("invalid OPTION_ABITS/WIDTH combination");
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endcase
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endgenerate
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endmodule
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module $__ANALOGDEVICES_LUTRAM_SDP_ (...);
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parameter INIT = 0;
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parameter OPTION_ABITS = 5;
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parameter WIDTH = 6;
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parameter BITS_USED = 0;
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input [WIDTH-1:0] PORT_W_WR_DATA;
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input [OPTION_ABITS-1:0] PORT_W_ADDR;
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input PORT_W_WR_EN;
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input PORT_W_CLK;
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output [WIDTH-1:0] PORT_R_RD_DATA;
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input [OPTION_ABITS-1:0] PORT_R_ADDR;
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function [(1 << OPTION_ABITS)-1:0] init_slice;
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input integer idx;
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integer i;
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for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
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init_slice[i] = INIT[i * WIDTH + idx];
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endfunction
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function [(2 << OPTION_ABITS)-1:0] init_slice2;
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input integer idx;
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integer i;
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for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
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init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
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endfunction
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generate
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case (OPTION_ABITS)
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5: if (WIDTH == 6)
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RAM32M
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#(
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.INIT_C(init_slice2(0)),
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.INIT_B(init_slice2(1)),
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.INIT_A(init_slice2(2)),
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)
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_TECHMAP_REPLACE_
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(
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.DOA(PORT_R_RD_DATA[5:4]),
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.DOB(PORT_R_RD_DATA[3:2]),
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.DOC(PORT_R_RD_DATA[1:0]),
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.DIA(PORT_W_WR_DATA[5:4]),
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.DIB(PORT_W_WR_DATA[3:2]),
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.DIC(PORT_W_WR_DATA[1:0]),
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.ADDRA(PORT_R_ADDR),
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.ADDRB(PORT_R_ADDR),
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.ADDRC(PORT_R_ADDR),
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.ADDRD(PORT_W_ADDR),
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.WE(PORT_W_WR_EN),
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.WCLK(PORT_W_CLK),
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);
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else
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RAM32M16
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#(
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.INIT_G(init_slice2(0)),
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.INIT_F(init_slice2(1)),
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.INIT_E(init_slice2(2)),
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.INIT_D(init_slice2(3)),
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.INIT_C(init_slice2(4)),
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.INIT_B(init_slice2(5)),
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.INIT_A(init_slice2(6)),
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)
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_TECHMAP_REPLACE_
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(
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.DOA(PORT_R_RD_DATA[13:12]),
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.DOB(PORT_R_RD_DATA[11:10]),
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.DOC(PORT_R_RD_DATA[9:8]),
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.DOD(PORT_R_RD_DATA[7:6]),
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.DOE(PORT_R_RD_DATA[5:4]),
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.DOF(PORT_R_RD_DATA[3:2]),
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.DOG(PORT_R_RD_DATA[1:0]),
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.DIA(PORT_W_WR_DATA[13:12]),
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.DIB(PORT_W_WR_DATA[11:10]),
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.DIC(PORT_W_WR_DATA[9:8]),
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.DID(PORT_W_WR_DATA[7:6]),
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.DIE(PORT_W_WR_DATA[5:4]),
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.DIF(PORT_W_WR_DATA[3:2]),
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.DIG(PORT_W_WR_DATA[1:0]),
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.ADDRA(PORT_R_ADDR),
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.ADDRB(PORT_R_ADDR),
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.ADDRC(PORT_R_ADDR),
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.ADDRD(PORT_R_ADDR),
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.ADDRE(PORT_R_ADDR),
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.ADDRF(PORT_R_ADDR),
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.ADDRG(PORT_R_ADDR),
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.ADDRH(PORT_W_ADDR),
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.WE(PORT_W_WR_EN),
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.WCLK(PORT_W_CLK),
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);
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6: if (WIDTH == 3)
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RAM64M
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#(
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.INIT_C(init_slice(0)),
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.INIT_B(init_slice(1)),
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.INIT_A(init_slice(2)),
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)
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_TECHMAP_REPLACE_
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(
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.DOA(PORT_R_RD_DATA[2]),
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.DOB(PORT_R_RD_DATA[1]),
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.DOC(PORT_R_RD_DATA[0]),
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.DIA(PORT_W_WR_DATA[2]),
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.DIB(PORT_W_WR_DATA[1]),
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.DIC(PORT_W_WR_DATA[0]),
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.ADDRA(PORT_R_ADDR),
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.ADDRB(PORT_R_ADDR),
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.ADDRC(PORT_R_ADDR),
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.ADDRD(PORT_W_ADDR),
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.WE(PORT_W_WR_EN),
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.WCLK(PORT_W_CLK),
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);
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else
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RAM64M8
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#(
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.INIT_G(init_slice(0)),
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.INIT_F(init_slice(1)),
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.INIT_E(init_slice(2)),
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.INIT_D(init_slice(3)),
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.INIT_C(init_slice(4)),
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.INIT_B(init_slice(5)),
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.INIT_A(init_slice(6)),
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)
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_TECHMAP_REPLACE_
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(
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.DOA(PORT_R_RD_DATA[6]),
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.DOB(PORT_R_RD_DATA[5]),
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.DOC(PORT_R_RD_DATA[4]),
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.DOD(PORT_R_RD_DATA[3]),
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.DOE(PORT_R_RD_DATA[2]),
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.DOF(PORT_R_RD_DATA[1]),
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.DOG(PORT_R_RD_DATA[0]),
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.DIA(PORT_W_WR_DATA[6]),
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.DIB(PORT_W_WR_DATA[5]),
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.DIC(PORT_W_WR_DATA[4]),
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.DID(PORT_W_WR_DATA[3]),
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.DIE(PORT_W_WR_DATA[2]),
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.DIF(PORT_W_WR_DATA[1]),
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.DIG(PORT_W_WR_DATA[0]),
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.ADDRA(PORT_R_ADDR),
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.ADDRB(PORT_R_ADDR),
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.ADDRC(PORT_R_ADDR),
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.ADDRD(PORT_R_ADDR),
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.ADDRE(PORT_R_ADDR),
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.ADDRF(PORT_R_ADDR),
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.ADDRG(PORT_R_ADDR),
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.ADDRH(PORT_W_ADDR),
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.WE(PORT_W_WR_EN),
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.WCLK(PORT_W_CLK),
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);
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default:
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$error("invalid OPTION_ABITS/WIDTH combination");
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endcase
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endgenerate
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endmodule
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