mirror of
https://github.com/YosysHQ/yosys
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109 lines
3.9 KiB
C++
109 lines
3.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/modtools.h"
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#include "kernel/qcsat.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OptMemPriorityPass : public Pass {
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OptMemPriorityPass() : Pass("opt_mem_priority", "remove priority relations between write ports that can never collide") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_mem_priority [selection]\n");
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log("\n");
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log("This pass detects cases where one memory write port has priority over another\n");
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log("even though they can never collide with each other -- ie. there can never be\n");
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log("a situation where a given memory bit is written by both ports at the same\n");
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log("time, for example because of always-different addresses, or mutually exclusive\n");
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log("enable signals. In such cases, the priority relation is removed.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n");
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extra_args(args, 1, design);
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ModWalker modwalker(design);
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int total_count = 0;
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for (auto module : design->selected_modules()) {
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modwalker.setup(module);
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for (auto &mem : Mem::get_selected_memories(module)) {
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bool mem_changed = false;
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QuickConeSat qcsat(modwalker);
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for (int i = 0; i < GetSize(mem.wr_ports); i++) {
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auto &wport1 = mem.wr_ports[i];
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for (int j = 0; j < GetSize(mem.wr_ports); j++) {
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auto &wport2 = mem.wr_ports[j];
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if (!wport1.priority_mask[j])
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continue;
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// No mixed width support — we could do it, but
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// that would complicate code and wouldn't help
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// anything since we run this pass before
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// wide ports are created in normal flow.
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if (wport1.wide_log2 != wport2.wide_log2)
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continue;
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// Two ports with priority, let's go.
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pool<std::pair<SigBit, SigBit>> checked;
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SigSpec addr1 = wport1.addr;
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SigSpec addr2 = wport2.addr;
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int abits = std::max(GetSize(addr1), GetSize(addr2));
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addr1.extend_u0(abits);
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addr2.extend_u0(abits);
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int addr_eq = qcsat.ez->vec_eq(qcsat.importSig(addr1), qcsat.importSig(addr2));
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bool ok = true;
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for (int k = 0; k < GetSize(wport1.data); k++) {
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SigBit wen1 = wport1.en[k];
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SigBit wen2 = wport2.en[k];
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if (checked.count({wen1, wen2}))
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continue;
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int wen1_sat = qcsat.importSigBit(wen1);
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int wen2_sat = qcsat.importSigBit(wen2);
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qcsat.prepare();
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if (qcsat.ez->solve(wen1_sat, wen2_sat, addr_eq)) {
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ok = false;
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break;
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}
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checked.insert({wen1, wen2});
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}
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if (ok) {
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total_count++;
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mem_changed = true;
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wport1.priority_mask[j] = false;
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}
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}
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}
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if (mem_changed)
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mem.emit();
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}
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}
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if (total_count)
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design->scratchpad_set_bool("opt.did_something", true);
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log("Performed a total of %d transformations.\n", total_count);
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}
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} OptMemPriorityPass;
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PRIVATE_NAMESPACE_END
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