mirror of
https://github.com/YosysHQ/yosys
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97 lines
3.2 KiB
Text
97 lines
3.2 KiB
Text
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yosys -- Yosys Open SYnthesis Suite
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===================================
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This is a framework for RTL synthesis tools. It is highly
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experimental and under construction. The goal for now is
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to implement an extensible Verilog-2005 synthesis tool.
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The aim of this tool is to generate valid logic netlists
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from HDL designs in a manner that allows for easy addition
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of extra synthesis passes. This tool does not aim at generating
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efficient logic netlists. This can be done by passing the
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output of Yosys to a low-level synthesis tool such as ABC.
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Yosys is free software licensed under the ISC license (a GPL
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compatible licence that is similar in terms to the MIT license
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or the 2-clause BSD license).
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Unsupported Verilog-2005 Features
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=================================
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The following Verilog-2005 features are not supported by
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yosys and there are currently no plans to add support
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for them:
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- Non-sythesizable language features as defined in
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IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
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- The "tri", "triand", "trior", "wand" and "wor" net types
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- The "library" and "configuration" source file formats
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- The "disable" and "primitive" statements
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- Latched logic (is synthesized as logic with feedback loops)
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Verilog Attributes and non-standard features
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============================================
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- The 'full_case' attribute on case statements is supported
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(also the non-standard "// synopsys full_case" directive)
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- The "// synopsys translate_off" and "// synopsys translate_on"
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directives are also supported (but the use of `ifdef .. `endif
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is strongly recommended instead).
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- The "nomem2reg" attribute on modules or arrays prohibits the
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automatic early conversion of arrays to seperate registers.
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- The "nolatches" attribute on modules or always-blocks
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prohibits the generation of logic-loops for latches. Instead
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all not explicitly assigned values default to x-bits.
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- In addition to the (* ... *) attribute syntax, yosys supports
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the non-standard {* ... *} attribute syntax to set default attributes
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for everything that comes after the {* ... *} statement. (Reset
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by adding an empty {* *} statement.) The preprocessor define
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__YOSYS_ENABLE_DEFATTR__ must be set in order for this featre to be active.
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TODOs / Open Bugs
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=================
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- Write "design and implementation of.." document
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- Add brief sourcecode documentation to:
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- Most passes and kernel functionalities
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- Implement missing Verilog 2005 features:
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- Signed constants
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- ROM modelling using "initial" blocks
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- Builtin primitive gates (and, nand, cmos, nmos, pmos, etc..)
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- Ignore what needs to be ignored (e.g. drive and charge strenghts)
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- Check standard vs. implementation to identify missing features
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- Actually use range information on parameters
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- Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees
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- TCL and Python interfaces to frontends, passes, backends and RTLIL
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- Additional internal cell types: $bitcount, $pla, $lut and $pmux
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- Subsystem for selecting stuff (and limiting scope of passes)
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- Support for registering designs (as collection of modules) to CellTypes
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- Kernel support for collections of cells (from input/output cones, etc)
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- Smarter resource sharing pass (add MUXes and get rid of duplicated cells)
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- FSM state encoding and technology mapping
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