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6503ad91c9
Add two new options to the splitnets pass: - `-ports_only`: Split only module ports, not internal signals. This is useful when you want to split ports for interface compatibility while keeping internal signals as multi-bit wires for better readability. - `-top_only`: Apply splitting only at the top module level, not in submodules. This is helpful for hierarchical designs where you need split signals only at the top-level interface. These options can be combined with existing flags: - `splitnets -ports_only`: Split all ports in all modules - `splitnets -ports_only -top_only`: Split ports only in top module - `splitnets -ports -top_only`: Split both ports and nets only in top Add comprehensive tests that verify wire/port counts for all flag combinations using a hierarchical design.
13 lines
306 B
Verilog
13 lines
306 B
Verilog
module bottom(input clk, input wire [1:0] i, output reg [1:0] q);
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reg [1:0] q1;
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always @(posedge clk) begin
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q1 <= i;
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q <= q1;
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end
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endmodule
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module top(input clk, input wire [1:0] i, output wire [1:0] q);
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wire [1:0] q1;
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bottom u1 (.clk(clk), .i(i), .q(q1));
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assign q = ~q1;
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endmodule
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