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https://github.com/YosysHQ/yosys
synced 2026-01-19 00:38:59 +00:00
6503ad91c9
Add two new options to the splitnets pass: - `-ports_only`: Split only module ports, not internal signals. This is useful when you want to split ports for interface compatibility while keeping internal signals as multi-bit wires for better readability. - `-top_only`: Apply splitting only at the top module level, not in submodules. This is helpful for hierarchical designs where you need split signals only at the top-level interface. These options can be combined with existing flags: - `splitnets -ports_only`: Split all ports in all modules - `splitnets -ports_only -top_only`: Split ports only in top module - `splitnets -ports -top_only`: Split both ports and nets only in top Add comprehensive tests that verify wire/port counts for all flag combinations using a hierarchical design.
63 lines
1.6 KiB
Tcl
63 lines
1.6 KiB
Tcl
yosys -import
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proc read_stats { file } {
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set fid [open $file]
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set result [read $fid]
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close $fid
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set ports 0
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set nets 0
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foreach line [split $result "\n"] {
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if [regexp {Number of wires:[ \t]+([0-9]+)} $line tmp n] {
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set nets [expr $nets + $n]
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}
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if [regexp {Number of ports:[ \t]+([0-9]+)} $line tmp n] {
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set ports [expr $ports + $n]
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}
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}
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return [list $nets $ports]
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}
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proc assert_count { type actual expected } {
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if {$actual != $expected} {
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puts "Error, $type count: $actual vs $expected expected"
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exit 1
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}
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}
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read_verilog test_splitnets.v
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hierarchy -auto-top
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procs
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design -save "pre"
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splitnets -ports_only -top_only
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write_verilog -noexpr "ports_only_in_top.v"
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tee -o "ports_only_in_top.txt" stat
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foreach {nets ports} [read_stats "ports_only_in_top.txt"] {}
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assert_count "nets" $nets 26
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assert_count "ports" $ports 16
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design -load "pre"
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splitnets -ports_only
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write_verilog -noexpr "ports_only_in_all.v"
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tee -o "ports_only_in_all.txt" stat
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foreach {nets ports} [read_stats "ports_only_in_all.txt"] {}
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assert_count "nets" $nets 30
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assert_count "ports" $ports 20
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design -load "pre"
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splitnets -ports -top_only
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write_verilog -noexpr "ports_nets_in_top.v"
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tee -o "ports_nets_in_top.txt" stat
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foreach {nets ports} [read_stats "ports_nets_in_top.txt"] {}
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assert_count "nets" $nets 30
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assert_count "ports" $ports 16
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design -load "pre"
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splitnets -ports
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write_verilog -noexpr "ports_nets_in_all.v"
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tee -o "ports_nets_in_all.txt" stat
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foreach {nets ports} [read_stats "ports_nets_in_all.txt"] {}
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assert_count "nets" $nets 40
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assert_count "ports" $ports 20
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exit 0
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