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yosys/backends/verilog
History
Alain Dargelas 64c8250b39
Merge 13ab5d4a67 into 8869ce61dc
2026-06-15 10:18:01 +02:00
..
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00
verilog_backend.cc Merge 13ab5d4a67 into 8869ce61dc 2026-06-15 10:18:01 +02:00
verilog_backend.h verilog backend: runtime optimization for keyword pool 2026-05-29 17:53:31 +00:00