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			132 lines
		
	
	
	
		
			3.8 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			132 lines
		
	
	
	
		
			3.8 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
| 
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| // Via http://www.edaplayground.com/s/6/591
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| // stackoverflow 20556634
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| // http://stackoverflow.com/questions/20556634/how-can-i-iteratively-create-buses-of-parameterized-size-to-connect-modules-also
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| 
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| // Code your design here
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| `define macro_args
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| `define indexed_part_select
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| 
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| module Multiplier_flat #(parameter M = 4, parameter N = 4)(
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| input [M-1:0] A, //Input A, size M
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| input [N-1:0] B, //Input B, size N
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| output [M+N-1:0] P );  //Output P (product), size M+N
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| 
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| /* Calculate LSB using Wolfram Alpha
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|  N==3 : http://www.wolframalpha.com/input/?i=0%2C+4%2C+9%2C+15%2C+...
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|  N==4 : http://www.wolframalpha.com/input/?i=0%2C+5%2C+11%2C+18%2C+26%2C+35%2C+...
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|  N==5 : http://www.wolframalpha.com/input/?i=0%2C+6%2C+13%2C+21%2C+30%2C+...
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|  */
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| `ifdef macro_args
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| // initial $display("Use Macro Args");
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| `define calc_pp_lsb(n) (((n)-1)*((n)+2*M)/2)
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| //`define calc_pp_msb(n) (`calc_pp_lsb(n+1)-1)
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| `define calc_pp_msb(n) ((n**2+(2*M+1)*n-2)/2)
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| //`define calc_range(n) `calc_pp_msb(n):`calc_pp_lsb(n)
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| `define calc_pp_range(n) `calc_pp_lsb(n) +: (M+n)
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| 
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| wire [`calc_pp_msb(N):0] PP;
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| assign PP[`calc_pp_range(1)] = { 1'b0 , { A & {M{B[0]}} } };
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| assign P = PP[`calc_pp_range(N)];
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| `elsif indexed_part_select
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| // initial $display("Use Indexed Part Select");
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| localparam MSB = (N**2+(2*M+1)*N-2)/2;
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| wire [MSB:0] PP;
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| assign PP[M:0] = { 1'b0 , { A & {M{B[0]}} } };
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| assign P = PP[MSB -: M+N];
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| `else
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| // initial $display("Use Worst Case");
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| localparam MSB = (N**2+(2*M+1)*N-2)/2;
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| wire [MSB:0] PP;
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| assign PP[M:0] = { 1'b0 , { A & {M{B[0]}} } };
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| assign P = PP[MSB : MSB+1-M-N];
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| `endif
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| 
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| genvar i;
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| generate
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| for (i=1; i < N; i=i+1)
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| begin: addPartialProduct
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|     wire [M+i-1:0] gA,gB,gS;
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|     wire Cout;
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|     assign gA = { A & {M{B[i]}} , {i{1'b0}} };
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|     `ifdef macro_args
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|     assign gB = PP[`calc_pp_range(i)];
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|     assign PP[`calc_pp_range(i+1)] = {Cout,gS};
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|     `elsif indexed_part_select
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|     assign gB = PP[(i-1)*(i+2*M)/2 +: M+i];
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|     assign PP[i*((i+1)+2*M)/2 +: M+i+1] = {Cout,gS};
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|     `else
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|     localparam LSB = (i-1)*(i+2*M)/2;
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|     localparam MSB = (i**2+(2*M+1)*i-2)/2;
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|     localparam MSB2 = ((i+1)**2+(2*M+1)*(i+1)-2)/2;
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|     assign gB = PP[MSB : LSB];
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|     assign PP[ MSB2 : MSB+1] = {Cout,gS};
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|     `endif
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|     RippleCarryAdder#(M+i) adder( .A(gA), .B(gB), .S(gS), .Cin (1'b0), .Cout(Cout) );
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| end
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| endgenerate
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| 
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| `ifdef macro_args
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| // Cleanup global space
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| `undef calc_pp_range
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| `undef calc_pp_msb
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| `undef calc_pp_lsb
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| `endif
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| endmodule
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| 
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| module Multiplier_2D #(parameter M = 4, parameter N = 4)(
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| input [M-1:0] A, //Input A, size M
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| input [N-1:0] B, //Input B, size N
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| output [M+N-1:0] P );  //Output P (product), size M+N
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| 
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| wire [M+N-1:0] PP [N-1:0];
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| 
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| // Note: bits PP[0][M+N-1:M+1] are never used. Unused bits are optimized out during synthesis
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| //assign PP[0][M:0] = { {1'b0} , { A & {M{B[0]}} } };
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| //assign PP[0][M+N-1:M+1] = {(N-1){1'b0}}; // uncomment to make probing readable
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| assign PP[0] = { {N{1'b0}} , { A & {M{B[0]}} } };
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| assign P = PP[N-1];
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| 
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| genvar i;
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| generate
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| for (i=1; i < N; i=i+1)
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| begin: addPartialProduct
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|     wire [M+i-1:0] gA,gB,gS; wire Cout;
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|     assign gA = { A & {M{B[i]}} , {i{1'b0}} };
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|     assign gB = PP[i-1][M+i-1:0];
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|     //assign PP[i][M+i:0] = {Cout,gS};
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|     //if (i+1<N) assign PP[i][M+N-1:M+i+1] = {(N-i){1'b0}}; // uncomment to make probing readable
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|     assign PP[i] = { {(N-i){1'b0}}, Cout, gS};
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|     RippleCarryAdder#(M+i) adder(
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|     	.A(gA), .B(gB), .S(gS), .Cin(1'b0), .Cout(Cout) );
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| end
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| endgenerate
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| 
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| //always@* foreach(S[i]) $display("S[%0d]:%b",i,S[i]);
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| 
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| endmodule
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| 
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| module RippleCarryAdder#(parameter N = 4)(A,B,Cin,S,Cout);
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| 
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| input [N-1:0] A;
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| input [N-1:0] B;
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| input Cin;
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| output [N-1:0] S;
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| output Cout;
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| wire [N:0] CC;
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| 
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| assign CC[0] = Cin;
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| assign Cout = CC[N];
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| genvar i;
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| generate
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| for (i=0; i < N; i=i+1)
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| begin: addbit
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|     FullAdder unit(A[i],B[i],CC[i],S[i],CC[i+1]);
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| end
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| endgenerate
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| 
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| endmodule
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| 
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| module FullAdder(input A,B,Cin, output wire S,Cout);
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| assign {Cout,S} = A+B+Cin;
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| endmodule
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