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All supported (and planned to be supported) GW5A series chips do not support the 2: Read-before-Write write mode. Here, we prohibit the generation of BSRAM with this mode. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
69 lines
1 KiB
Text
69 lines
1 KiB
Text
ram block $__GOWIN_SP_ {
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abits 14;
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widths 1 2 4 9 18 36 per_port;
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cost 128;
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init no_undef;
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port srsw "A" {
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clock posedge;
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clken;
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option "RESET_MODE" "SYNC" {
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rdsrst zero ungated;
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}
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option "RESET_MODE" "ASYNC" {
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rdarst zero;
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}
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rdinit zero;
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portoption "WRITE_MODE" 0 {
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rdwr no_change;
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}
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portoption "WRITE_MODE" 1 {
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rdwr new;
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}
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}
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}
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ram block $__GOWIN_DP_ {
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abits 14;
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widths 1 2 4 9 18 per_port;
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cost 128;
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init no_undef;
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port srsw "A" "B" {
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clock posedge;
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clken;
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option "RESET_MODE" "SYNC" {
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rdsrst zero ungated;
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}
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option "RESET_MODE" "ASYNC" {
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rdarst zero;
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}
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rdinit zero;
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portoption "WRITE_MODE" 0 {
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rdwr no_change;
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}
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portoption "WRITE_MODE" 1 {
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rdwr new;
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}
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}
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}
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ram block $__GOWIN_SDP_ {
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abits 14;
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widths 1 2 4 9 18 36 per_port;
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cost 128;
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init no_undef;
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port sr "R" {
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clock posedge;
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clken;
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option "RESET_MODE" "SYNC" {
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rdsrst zero ungated;
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}
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option "RESET_MODE" "ASYNC" {
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rdarst zero;
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}
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rdinit zero;
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}
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port sw "W" {
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clock posedge;
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clken;
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}
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}
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