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All supported (and planned to be supported) GW5A series chips do not support the 2: Read-before-Write write mode. Here, we prohibit the generation of BSRAM with this mode. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
15 lines
905 B
Makefile
15 lines
905 B
Makefile
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OBJS += techlibs/gowin/synth_gowin.o
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra_gw1n.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra_gw2a.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra_gw5a.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map_gw5a.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_gw5a.txt))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt))
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