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yosys/techlibs/xilinx
2025-07-22 10:38:38 +00:00
..
tests Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
abc9_model.v
arith_map.v
brams_defs.vh
brams_xc2v.txt
brams_xc2v_map.v
brams_xc3sda.txt
brams_xc3sda_map.v
brams_xc4v.txt
brams_xc4v_map.v
brams_xc5v_map.v
brams_xc6v_map.v
brams_xcu_map.v
brams_xcv.txt
brams_xcv_map.v
cells_map.v Clearer diff for the all-x corner case 2025-04-07 07:55:30 +02:00
cells_sim.v
cells_xtra.py
cells_xtra.v
ff_map.v
lut_map.v
lutrams_xc5v.txt
lutrams_xc5v_map.v
lutrams_xcu.txt
lutrams_xcv.txt
lutrams_xcv_map.v
Makefile.inc pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
mux_map.v
synth_xilinx.cc
urams.txt URAM mapping : Add test for 2048 x 144b 2025-05-10 14:53:56 +02:00
urams_map.v URAM mapping : Fix port indexes according to Yosys warnings 2025-05-09 15:09:11 +02:00
xc3s_mult_map.v
xc3sda_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_dsp_map.v
xc7_dsp_map.v
xcu_dsp_map.v
xilinx_dffopt.cc
xilinx_dsp.cc pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_dsp.pmg pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_dsp48a.pmg pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_dsp_cascade.pmg pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_dsp_CREG.pmg pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_srl.cc pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_srl.pmg pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00