mirror of
https://github.com/YosysHQ/yosys
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3a153f99db
Updates code examples, removing `counter_outputs.ys` in favour of a single script. Also adds a .gitignore for the output file `synth.v`. `example_synth.rst` still pending updated example.
32 lines
581 B
Plaintext
32 lines
581 B
Plaintext
# read design
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read_verilog counter.v
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hierarchy -check -top counter
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show -notitle -format dot -prefix counter_00
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# the high-level stuff
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proc; opt
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memory; opt
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fsm; opt
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show -notitle -format dot -prefix counter_01
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# mapping to internal cell library
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techmap; opt
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splitnets -ports;; show -notitle -format dot -prefix counter_02
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# mapping flip-flops to mycells.lib
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dfflibmap -liberty mycells.lib
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# mapping logic to mycells.lib
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abc -liberty mycells.lib
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# cleanup
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clean
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show -notitle -lib mycells.v -format dot -prefix counter_03
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# write synthesized design
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write_verilog synth.v
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